Dear Haavard Skinnemoen, In message <[EMAIL PROTECTED]> you wrote: > > Btw, that command won't actually test the SDRAM since do_mem_loop() > accesses cacheable memory. The first access will load the data into the
This depends on your board configuration. Date cache may be globally enabled or not, or anabled or not for the specific address range in question. > dcache, and subsequent accesses will simply read it from the dcache and > not cause any memory accesses. Maybe, maybe not. > What is this command supposed to test anyway? It's highly unlikely that > it will find any SDRAM problems by simply reading an address without > checking the result... The command is not restricted on reading from SDRAM, but works on any other address ranges, too. SOmetimes it's pretty helpful to see read cycles from a certain address (range) without anything other traffic on the bus - it makes it easy to analyze timings and signal quality, etc. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] "Faith: not *wanting* to know what is true." - Friedrich Nietzsche _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
