Dear Adam Graham, In message <[EMAIL PROTECTED]> you wrote: > After changing SDRAM_CLKTR phase value rerun the memory preload > initialization sequence (INITPLR) to reset and relock the memory DLL. > Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects > the phase relationship of the internal, to the PPC chip, and external, to the > PPC chip, versions of MEMCLK_OUT.
Line too long. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] Keep your head and your heart going in the right direction and you will not have to worry about your feet. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
