Hi, > In message <[EMAIL PROTECTED]> you wrote: >> >> Interestingly enough, dcbst is a *data* cache store, run in the *icache* >> flush routine. I assume this is intended to flush out any instructions >> that are stuck in the dcache due to writes (self modifying code and/or >> loaded/copied code). I would *speculate* that the address of the stuff >> in your dcache no longer points to valid memory. > > Also let's keep in mind that cache flushing means accessing the RAM in > burst mode, so have a look at FAQ # 1.
1. You were right Wolfgang, I still had issue with my SDRAM. It seems that I misunderstand the DR field of BR SDRAM register as setting it produces "random" failures in MMU init. I'm however using ECC, therefore I will have to understand exactly why it is not needed... SDRAM init is really unforgiving ! 2. I forgot to add appropriate #define CONFIG_OF_BOARD_SETUP and custom RAM size code settings for my custom board, therefore the RAM size in Linux fdt was set to 0... Not good at all and hangs very early without much details. With this, my kernel completes its init (and hangs in NFS mount, but this is another story...). At last, I have some doubt about the fdt "timebase-frequency" value. It seems to be set to (bus_clk / 4) on mpc8260, but I cannot find in the mpc8270 (mpc8280) user manual any confirmation. Does this value only depends on cpu or could the board have any influence on it ? I know this is related to the decrementer register but I miss some basic understanding here. Anyway, thanks for your advices. Regards, Rémi _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
