Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
---
cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++----
include/asm-ppc/ppc4xx-sdram.h | 5 +++++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index f1d7684..995d5fe 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long
*dimm_populated,
/*
* Set optimal value for Memory Queue HB/LL Configuration registers
*/
- mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
- SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
- mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
- SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+ mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+ SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+ SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+ mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+ SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+ SDRAM_CONF1LL_RPLM);
mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
#endif
}
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 8efa557..98faced 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -272,8 +272,11 @@
#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable -
Bit 12 */
#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable -
Bit 13 */
#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits
16..19 */
#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20
*/
#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable -
Bit 21 */
+#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits
22..24 */
+#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status
HB */
#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error
address upper 32 HB */
@@ -284,8 +287,10 @@
#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline
Disable - Bit 12 */
#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline
Disable - Bit 13 */
#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit
14 */
+#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1
- Bits 16..19 */
#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable
- Bit 20 */
#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through
Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status
LL */
#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error
address upper 32 LL */
--
1.5.6.1
Regards, Yuri
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
