I hit the same trap as Lucas with my HV (netcup.de). bios0 at mainbus0: SMBIOS rev. 2.8 @ 0xf5900 (10 entries) bios0: vendor netcup version "RS 1000 G9 Plus" date 12/17/2020 bios0: netcup KVM Server acpi0 at bios0: ACPI 1.0 acpi0: sleep states S5 acpi0: tables DSDT FACP APIC acpi0: wakeup devices acpitimer0 at acpi0: 3579545 Hz, 24 bits acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: AMD EPYC 7702P 64-Core Processor, 1996.52 MHz, 17-31-00 cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,HV,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,CPCTR,FSGSBASE,TSC_ADJUST,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,SHA,UMIP,IBRS,IBPB,STIBP,SSBD,IBPB,IBRS,STIBP,SSBD,VIRTSSBD,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu0: 64KB 64b/line 2-way D-cache, 64KB 64b/line 2-way I-cache cpu0: 512KB 64b/line 16-way L2 cache cpu0: smt 0, core 0, package 0
https://ibb.co/gZPtLZb https://ibb.co/sgnTsPb Based on your diff below the following diff applies on -stable and works for me. Index: cpu.c =================================================================== RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v retrieving revision 1.165 diff -u -p -r1.165 cpu.c --- cpu.c 9 Mar 2023 13:17:28 -0000 1.165 +++ cpu.c 25 Jul 2023 06:17:59 -0000 @@ -1181,7 +1181,8 @@ cpu_fix_msrs(struct cpu_info *ci) * This MSR is available on all AMD families >= 10h, except 11h * where LFENCE is always serializing. */ - if (family >= 0x10 && family != 0x11) { + if (family >= 0x10 && family != 0x11 && + (cpu_ecxfeature & CPUIDECX_HV) == 0) { msr = rdmsr(MSR_DE_CFG); if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { msr |= DE_CFG_SERIALIZE_LFENCE; On Mon Jul 24, 2023 at 10:25:29PM -0600, Theo de Raadt wrote: > Would like to know if this patch helps anyone with this type of > problem. > > Index: sys/arch/amd64/amd64/cpu.c > =================================================================== > RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v > retrieving revision 1.172 > diff -u -p -u -r1.172 cpu.c > --- sys/arch/amd64/amd64/cpu.c 24 Jul 2023 14:53:58 -0000 1.172 > +++ sys/arch/amd64/amd64/cpu.c 25 Jul 2023 03:28:35 -0000 > @@ -1216,7 +1216,8 @@ cpu_fix_msrs(struct cpu_info *ci) > if (msr != nmsr) > wrmsr(MSR_DE_CFG, nmsr); > } > - if (family == 0x17 && ci->ci_model >= 0x31) { > + if (family == 0x17 && ci->ci_model >= 0x31 && > + (cpu_ecxfeature & CPUIDECX_HV) == 0) { > nmsr = msr = rdmsr(MSR_DE_CFG); > nmsr |= DE_CFG_SERIALIZE_9; > if (msr != nmsr) > Index: sys/arch/i386/i386/machdep.c > =================================================================== > RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v > retrieving revision 1.664 > diff -u -p -u -r1.664 machdep.c > --- sys/arch/i386/i386/machdep.c 24 Jul 2023 14:54:00 -0000 1.664 > +++ sys/arch/i386/i386/machdep.c 25 Jul 2023 03:28:29 -0000 > @@ -1993,7 +1993,8 @@ identifycpu(struct cpu_info *ci) > if (msr != nmsr) > wrmsr(MSR_DE_CFG, nmsr); > } > - if (family == 0x17 && ci->ci_model >= 0x31) { > + if (family == 0x17 && ci->ci_model >= 0x31 && > + (cpu_ecxfeature & CPUIDECX_HV) == 0) { > nmsr = msr = rdmsr(MSR_DE_CFG); > nmsr |= DE_CFG_SERIALIZE_9; > if (msr != nmsr) >
