com.c: ASIX AX99100(PCIe UART) probed FIFO depth=0 issue

[SASANO Takayoshi]

Hi,

At least 6.9 and 7.0 (and -current) sometimes shows a dmesg that:

  puc1 at pci1 dev 0 function 1 "ASIX AX99100" rev 0x00: ports: 16 com
  com5 at puc1 port 0 apic 1 int 1: st16650, 32 byte fifo
  com5: probed fifo depth: 0 bytes

In sys/dev/ic/com.c:com_fifo_probe(), I found that transmitted data to
determine FIFO depth is not received. And, a bit delay is required after
TX/RX FIFO reset.

Simply adding com_read_reg(sc, com_iir) resolves this issue on my PC,
but I think delay(100) may be better like other resetting FIFO.

Here is the diff, any comments will be welcomed.

Index: com.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/com.c,v
retrieving revision 1.174
diff -u -p -r1.174 com.c
--- com.c       6 May 2021 20:35:21 -0000       1.174
+++ com.c       16 Oct 2021 03:05:54 -0000
@@ -1562,6 +1562,7 @@ com_fifo_probe(struct com_softc *sc)
                fifo |= FIFO_ENABLE_64BYTE;
 
        com_write_reg(sc, com_fifo, fifo);
+       delay(100);
 
        for (len = 0; len < 256; len++) {
                com_write_reg(sc, com_data, (len + 1));

-- 
SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net>