On Mon, Dec 16, 2019 at 03:19:30PM +0100, Claudio Jeker wrote: > On Mon, Dec 16, 2019 at 08:46:21AM -0500, Bryan Steele wrote: > > On Mon, Dec 16, 2019 at 12:37:51PM +0100, Claudio Jeker wrote: > > > This diff should add support for newer smbus controllers used on newer AMD > > > chipsets. Especially Hudson-2 and Kerncz based chipsets. On my Ryzen 5 the > > > iic(4) busses attach but there is nothing detected on them (well possible > > > that I missed something). I also implemented the up to 4 busses available > > > on chipsets of the SBx00 series (on Hudson-2 and Kerncz only 2 ports). > > > > > > I would be interested if on systems with Ryzen CPUs something attaches to > > > those iic(4) busses. Could be that I missed something and fail to properly > > > access the bus. > > > -- > > > :wq Claudio > > > > I had a similar diff (except without the additional busses), and didn't > > go further as none of my machines show any devices either (not even > > spdmem(4)), I assumed it was on another bus.. but maybe it's on an > > entirely different controller now. > > > > bios0: vendor American Megatrends Inc. version "5220" date 09/11/2019 > > bios0: ASUSTeK COMPUTER INC. PRIME X470-PRO > > .. > > piixpm0 at pci0 dev 20 function 0 "AMD FCH SMBus" rev 0x59: polling > > iic0 at piixpm0 > > iic1 at piixpm0 > > > > Otherwise, diff "looks" ok. I'll try it on my MateBook later, but > > I have a feeling it was the same story. > > > > Otherwise, diff "looks" ok. > > > > spdmem(4) needs an update to support DDR4 to show up on the bus. I did not > realize that until after I sent this out. This is why spdmem(4) does not > attach. I'm working now on spdmem(4) support for DDR4.
Oh interesting. I hadn't considered that. Look forward to testing that then! :-) > -- > :wq Claudio >
