> Date: Thu, 9 May 2019 22:26:52 +1000
> From: Jonathan Gray <[email protected]>
>
> On Thu, May 09, 2019 at 07:45:37AM +0200, Alexandre Ratchov wrote:
> > In the intel_gtt_chipset_setup() routine, called at initialization,
> > the driver maps pci space for certain chip models only, but later in
> > intel_gtt_chipset_flush() it calls bus_space_write() on it in cases
> > it's not initialized.
> >
> > This results in crashes during boot with "Pineview" generation chips,
> > which are "gen == 3", but, according to intel_gtt_chipset_setup() have
> > no flush page mechanism.
> >
> > Fix this by adding a flag indicating whether the feature is available
> > or not. Then use the flag to check if it's OK to write to the pci
> > space. This is the what the driver did before the 14 april update.
> >
> > OK?
> >
> > FWIW, first it looked surprising to do nothing in
> > intel_gtt_chipset_flush(), so I also tried to call the "gen < 3"
> > code. It works as well.
>
> intel_gtt_chipset_setup() is wrong the 915/945 ifp setup should be used
> on pineview as well. g33 is the only gen3 that is different.
>
> This was apparently missed in
>
> ----------------------------
> revision 1.78
> date: 2010/05/12 16:20:00; author: oga; state: Exp; lines: +2 -0;
> Add Pineview M to intagp and inteldrm.
>
> Tested (and initial tweaked diff) from Erik Mugele; thanks!
> ----------------------------
>
> The original ifp setup bits were added in sys/dev/pci/drm/i915_drv.c
> rev 1.45 and the ifp setup we use today come from that.
Looks good to me.
> Index: intel_gtt.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_gtt.c,v
> retrieving revision 1.2
> diff -u -p -r1.2 intel_gtt.c
> --- intel_gtt.c 14 Apr 2019 10:14:52 -0000 1.2
> +++ intel_gtt.c 9 May 2019 12:07:01 -0000
> @@ -130,11 +130,10 @@ intel_gtt_chipset_setup(struct drm_devic
> }
>
> /* Set up the IFP for chipset flushing */
> - if (IS_I915G(dev_priv) || IS_I915GM(dev_priv) || IS_I945G(dev_priv) ||
> - IS_I945GM(dev_priv)) {
> - i915_alloc_ifp(dev_priv, &bpa);
> - } else if (INTEL_GEN(dev_priv) >= 4 || IS_G33(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 4 || IS_G33(dev_priv)) {
> i965_alloc_ifp(dev_priv, &bpa);
> + } else if (INTEL_GEN(dev_priv) == 3) {
> + i915_alloc_ifp(dev_priv, &bpa);
> } else {
> int nsegs;
> /*
>
>
