There is a new rgepy(4) variant (rev. 6, RTL8211F). Unfortunately
they moved the status register around on this new chip and also
twiddled the bits. Here is a diff that handles that. Somewhat
inspired by FreeBSD but I didn't add some of the workarounds tat
disable EEE and power save mode that are found in their rgephy(4). So
far it seems I don't really need those for my Rock64 board.
ok?
Index: dev/mii/rgephy.c
===================================================================
RCS file: /cvs/src/sys/dev/mii/rgephy.c,v
retrieving revision 1.39
diff -u -p -r1.39 rgephy.c
--- dev/mii/rgephy.c 11 Mar 2017 13:40:46 -0000 1.39
+++ dev/mii/rgephy.c 26 Feb 2018 20:59:48 -0000
@@ -255,6 +255,11 @@ setit:
sc->mii_ticks = 0;
break;
}
+ } else if (sc->mii_rev == RGEPHY_8211F) {
+ reg = PHY_READ(sc, RGEPHY_F_SR);
+ if (reg & RGEPHY_F_SR_LINK) {
+ sc->mii_ticks = 0;
+ }
} else {
reg = PHY_READ(sc, RGEPHY_SR);
if (reg & RGEPHY_SR_LINK) {
@@ -309,6 +314,10 @@ rgephy_status(struct mii_softc *sc)
bmsr = PHY_READ(sc, RL_GMEDIASTAT);
if (bmsr & RL_GMEDIASTAT_LINK)
mii->mii_media_status |= IFM_ACTIVE;
+ } else if (sc->mii_rev == RGEPHY_8211F) {
+ bmsr = PHY_READ(sc, RGEPHY_F_SR);
+ if (bmsr & RGEPHY_F_SR_LINK)
+ mii->mii_media_status |= IFM_ACTIVE;
} else {
bmsr = PHY_READ(sc, RGEPHY_SR);
if (bmsr & RGEPHY_SR_LINK)
@@ -340,6 +349,20 @@ rgephy_status(struct mii_softc *sc)
mii->mii_media_active |= IFM_10_T;
if (bmsr & RL_GMEDIASTAT_FDX)
+ mii->mii_media_active |= mii_phy_flowstatus(sc) |
+ IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+ } else if (sc->mii_rev == RGEPHY_8211F) {
+ bmsr = PHY_READ(sc, RGEPHY_F_SR);
+ if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_1000MBPS)
+ mii->mii_media_active |= IFM_1000_T;
+ else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_100MBPS)
+ mii->mii_media_active |= IFM_100_TX;
+ else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_10MBPS)
+ mii->mii_media_active |= IFM_10_T;
+
+ if (bmsr & RGEPHY_F_SR_FDX)
mii->mii_media_active |= mii_phy_flowstatus(sc) |
IFM_FDX;
else
Index: dev/mii/rgephyreg.h
===================================================================
RCS file: /cvs/src/sys/dev/mii/rgephyreg.h,v
retrieving revision 1.8
diff -u -p -r1.8 rgephyreg.h
--- dev/mii/rgephyreg.h 19 Jul 2015 06:35:18 -0000 1.8
+++ dev/mii/rgephyreg.h 26 Feb 2018 20:59:48 -0000
@@ -36,6 +36,10 @@
#ifndef _DEV_MII_RGEPHYREG_H_
#define _DEV_MII_RGEPHYREG_H_
+#define RGEPHY_8211B 2
+#define RGEPHY_8211C 3
+#define RGEPHY_8211F 6
+
/*
* Realtek 8169S/8110S gigE PHY registers
*/
@@ -52,6 +56,7 @@
#define RGEPHY_CR_ALDPS 0x0004 /* RTL8251 only */
#define RGEPHY_CR_JABBER_DIS 0x0001
+/* RTL8211B(L)/RTL8211C(L) */
#define RGEPHY_SR 0x11 /* PHY Specific Status */
#define RGEPHY_SR_SPEED_1000MBPS 0x8000
#define RGEPHY_SR_SPEED_100MBPS 0x4000
@@ -65,6 +70,16 @@
#define RGEPHY_SR_ALDPS 0x0008 /* RTL8211C(L) only */
#define RGEPHY_SR_JABBER 0x0001 /* Jabber */
#define RGEPHY_SR_SPEED(X) ((X) & RGEPHY_SR_SPEED_MASK)
+
+/* RTL8211F */
+#define RGEPHY_F_SR 0x1A /* PHY Specific Status */
+#define RGEPHY_F_SR_SPEED_1000MBPS 0x0020
+#define RGEPHY_F_SR_SPEED_100MBPS 0x0010
+#define RGEPHY_F_SR_SPEED_10MBPS 0x0000
+#define RGEPHY_F_SR_SPEED_MASK 0x0030
+#define RGEPHY_F_SR_FDX 0x0004
+#define RGEPHY_F_SR_LINK 0x0002
+#define RGEPHY_F_SR_SPEED(X) ((X) & RGEPHY_F_SR_SPEED_MASK)
#define RGEPHY_LC 0x18 /* PHY LED Control Register */
#define RGEPHY_LC_P2 0x1A /* PHY LED Control Register, Page 2 */
