AR9380 devices are currently not supported by our athn(4).
There is code for them in the driver, but this code does not work yet.
This diff makes monitor mode work with an AR9380 device I have lying around.
athn0 at pci1 dev 0 function 0 "Atheros AR9300" rev 0x01: apic 2 int 16
athn0: AR9380 rev 3 (3T3R), ROM rev 0, address xx:xx:xx:xx:xx:xx
This means it can now receive packets (transmit is still broken).
The fixes are:
1) The Rx done bit is in word 11 of the Rx descriptor, not in word 1.
2) The card sends an RXEOL interrupt when it receives a packet.
3) Rx enable bits in the config registers differ from older devices
(the common code in athn.c looks at these bits).
I have cross-checked these changes with Linux ath9k.
To test this diff, PCI_PRODUCT_ATHEROS_AR9300 must also be added
to the PCI device list in if_athn_pci.c (not included here since
I doubt anyone will bother at this point).
ok?
Index: ic/ar9003.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar9003.c,v
retrieving revision 1.45
diff -u -p -r1.45 ar9003.c
--- ic/ar9003.c 8 Mar 2017 12:02:41 -0000 1.45
+++ ic/ar9003.c 18 May 2017 00:11:06 -0000
@@ -934,7 +934,7 @@ ar9003_rx_process(struct athn_softc *sc,
BUS_DMASYNC_POSTREAD);
ds = mtod(bf->bf_m, struct ar_rx_status *);
- if (!(ds->ds_status1 & AR_RXS1_DONE))
+ if (!(ds->ds_status11 & AR_RXS11_DONE))
return (EBUSY);
/* Check that it is a valid Rx status descriptor. */
@@ -1345,7 +1345,7 @@ ar9003_intr(struct athn_softc *sc)
#endif
if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
ar9003_rx_intr(sc, ATHN_QID_LP);
- if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
+ if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR | AR_ISR_RXEOL))
ar9003_rx_intr(sc, ATHN_QID_LP);
if (intr & AR_ISR_HP_RXOK)
ar9003_rx_intr(sc, ATHN_QID_HP);
Index: ic/ar9003reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar9003reg.h,v
retrieving revision 1.8
diff -u -p -r1.8 ar9003reg.h
--- ic/ar9003reg.h 20 Oct 2012 09:53:32 -0000 1.8
+++ ic/ar9003reg.h 18 May 2017 00:11:06 -0000
@@ -1157,7 +1157,6 @@ struct ar_rx_status {
#define AR_RXI_DESC_ID_S 16
/* Bits for ds_status1. */
-#define AR_RXS1_DONE 0x00000001
#define AR_RXS1_RATE_M 0x000003fc
#define AR_RXS1_RATE_S 2
@@ -1175,6 +1174,7 @@ struct ar_rx_status {
#define AR_RXS5_RSSI_COMBINED_S 24
/* Bits for ds_status11. */
+#define AR_RXS11_DONE 0x00000001
#define AR_RXS11_FRAME_OK 0x00000002
#define AR_RXS11_CRC_ERR 0x00000004
#define AR_RXS11_DECRYPT_CRC_ERR 0x00000008
Index: ic/athnreg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/athnreg.h,v
retrieving revision 1.19
diff -u -p -r1.19 athnreg.h
--- ic/athnreg.h 18 Dec 2016 14:34:20 -0000 1.19
+++ ic/athnreg.h 18 May 2017 00:11:06 -0000
@@ -253,7 +253,7 @@
/* Bits for AR_CR. */
-#define AR_CR_RXE 0x00000004
+#define AR_CR_RXE (AR_SREV_9380_20_OR_LATER(sc) ? 0x000c : 0x0004)
#define AR_CR_RXD 0x00000020
#define AR_CR_SWI 0x00000040
