> On 25 Apr 2017, at 6:18 am, Mark Kettenis <mark.kette...@xs4all.nl> wrote: > >> Date: Mon, 24 Apr 2017 16:01:39 -0400 >> From: Dale Rahn <dr...@dalerahn.com> >> >> The below code is set up to attach and identify processors for arm64 >> currently it only identifies model, not cache size, but that can be added >> later. It is set up to attach secondary processors later (for when SMP >> is present). > > I don't think this cpubus(4) device makes much sense. We don't have > something like that on other FDT/OpenFirmware architectures.
there’s this: mainbus0 at root: SPARC Enterprise M4000 Server cmp0 at mainbus0 core0 at cmp0 cpu0 at core0: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu0: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) cpu1 at core0: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu1: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) core1 at cmp0 cpu2 at core1: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu2: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) cpu3 at core1: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu3: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) cmp1 at mainbus0 core2 at cmp1 cpu4 at core2: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu4: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) cpu5 at core2: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu5: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) core3 at cmp1 cpu6 at core3: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu6: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l) cpu7 at core3: FJSV,SPARC64-VI (rev 9.3) @ 2150 MHz cpu7: physical 128K instruction (64 b/l), 128K data (64 b/l), 5120K external (256 b/l)
