The functions that clean/invalidate the caches by virtual address,
bail out after cleaning 32k worth of data. The 32k matches the L1
cache of most of the CPUs we current run on. But the Cortex-A7 has an
integrated L2 cache that is larger. And if you only flush it
partially you may get into trouble. And now that we actually use the
cache that matters. Many of the more recent ARMv7 CPUs include such a
L2 cache. And some of them even have L1 caches that are larger than
32k. So drop the shortcut and simply clean/invalidate what we were
asked to clean/invalidate. Most of the calls should be covering a
single page or less anyway.
This fixes the core dumps and illegal instructions that I see when
booting from a SATA disk.
ok?
Index: arch/arm/arm/cpufunc_asm_armv7.S
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v
retrieving revision 1.13
diff -u -p -r1.13 cpufunc_asm_armv7.S
--- arch/arm/arm/cpufunc_asm_armv7.S 6 Aug 2016 16:46:25 -0000 1.13
+++ arch/arm/arm/cpufunc_asm_armv7.S 15 Aug 2016 19:45:53 -0000
@@ -103,8 +103,6 @@ ENTRY(armv7_tlb_flushD)
i_inc .req r3
ENTRY(armv7_icache_sync_range)
ldr ip, .Larmv7_icache_line_size
- cmp r1, #0x8000
- movcs r1, #0x8000 /* XXX needs to match cache size... */
ldr ip, [ip]
sub r1, r1, #1 /* Don't overrun */
sub r3, ip, #1
@@ -136,8 +134,6 @@ ENTRY(armv7_icache_sync_all)
ENTRY(armv7_dcache_wb_range)
ldr ip, .Larmv7_dcache_line_size
- cmp r1, #0x8000
- movcs r1, #0x8000 /* XXX needs to match cache size... */
ldr ip, [ip]
sub r1, r1, #1 /* Don't overrun */
sub r3, ip, #1
@@ -155,8 +151,6 @@ ENTRY(armv7_dcache_wb_range)
ENTRY(armv7_idcache_wbinv_range)
ldr ip, .Larmv7_idcache_line_size
- cmp r1, #0x8000
- movcs r1, #0x8000 /* XXX needs to match cache size... */
ldr ip, [ip]
sub r1, r1, #1 /* Don't overrun */
sub r3, ip, #1
@@ -177,8 +171,6 @@ ENTRY(armv7_idcache_wbinv_range)
ENTRY(armv7_dcache_wbinv_range)
ldr ip, .Larmv7_dcache_line_size
- cmp r1, #0x8000
- movcs r1, #0x8000 /* XXX needs to match cache size... */
ldr ip, [ip]
sub r1, r1, #1 /* Don't overrun */
sub r3, ip, #1
@@ -198,8 +190,6 @@ ENTRY(armv7_dcache_wbinv_range)
ENTRY(armv7_dcache_inv_range)
ldr ip, .Larmv7_dcache_line_size
- cmp r1, #0x8000
- movcs r1, #0x8000 /* XXX needs to match cache size... */
ldr ip, [ip]
sub r1, r1, #1 /* Don't overrun */
sub r3, ip, #1
