> Date: Sun, 1 May 2016 22:45:44 +1000
> From: Jonathan Gray <[email protected]>
>
> On Sun, May 01, 2016 at 01:50:59PM +0200, Mark Kettenis wrote:
> > > Date: Sun, 1 May 2016 13:40:31 +1000
> > > From: Jonathan Gray <[email protected]>
> > >
> > > On Sat, Apr 30, 2016 at 09:50:15PM +0200, Mark Kettenis wrote:
> > > > The diff below adds support for changing the bus width to the sdmmc
> > > > subsystem and the sdhc(4) controller. By default controllers and card
> > > > use a 1-bit bus. But most SD cards actually have support fora 4-bit
> > > > bus. This can be checked by looking atthe SCR register. In theory
> > > > using the 4-bit bus quadruples the data rate to and from the card.
> > > >
> > > > With this diff the raw disk transferrate of the sdhc(4) controller in
> > > > te PC-Engines APU2 goes up from 1.5 MB/s to 5.5 MB/s.
> > > >
> > > > ok?
> > >
> > > diff below for imx/omap.
> > >
> > > imx sdhc fails with
> > >
> > > sdmmc0: SD_SEND_SCR send failed
> > > sdmmc0: mem init failed
> > > scsibus2 at sdmmc0: 2 targets, initiator 0
> > > sd1 at scsibus2 targ 1 lun 0: <SD/MMC, Drive #01, > SCSI2 0/direct fixed
> > > sd1: 7655MB, 512 bytes/sector, 15677440 sectors
> > >
> > > but it is known to have errors sending block io commands
> > > so perhaps that isn't so surprising.
> >
> > What type of card are you using?
> >
> > In any case, the SD_SEND_SCR command does rely on block io, so if that
> > doesn't work reliably, then it isn't too surprising that things fail.
>
> imxesdhc is known to not work, I tried to figure out it at one
> point but never got anywhere. I don't think it ever really worked
> for patrick either.
>
> >
> > The omap code looks wrong. As far as I can see there is a DTW bit
> > there as well to switch between 1-bit and 4-bit mode.
>
> Ah yes, updated diff:
I've committed my diff. This looks ok as well, but it won't be used
until you also set the SMC_CAPS_4BIT_MODE capability when attaching
sdmmc.
> Index: ommmc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/omap/ommmc.c,v
> retrieving revision 1.15
> diff -u -p -r1.15 ommmc.c
> --- ommmc.c 10 Jan 2016 14:11:43 -0000 1.15
> +++ ommmc.c 1 May 2016 12:40:52 -0000
> @@ -229,6 +229,7 @@ int ommmc_host_maxblklen(sdmmc_chipset_h
> int ommmc_card_detect(sdmmc_chipset_handle_t);
> int ommmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
> int ommmc_bus_clock(sdmmc_chipset_handle_t, int);
> +int ommmc_bus_width(sdmmc_chipset_handle_t, int);
> void ommmc_card_intr_mask(sdmmc_chipset_handle_t, int);
> void ommmc_card_intr_ack(sdmmc_chipset_handle_t);
> void ommmc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
> @@ -260,6 +261,7 @@ struct sdmmc_chip_functions ommmc_functi
> /* bus power and clock frequency */
> ommmc_bus_power,
> ommmc_bus_clock,
> + ommmc_bus_width,
> /* command execution */
> ommmc_exec_command,
> /* card interrupt */
> @@ -693,6 +695,32 @@ ommmc_bus_clock(sdmmc_chipset_handle_t s
> ret:
> splx(s);
> return (error);
> +}
> +
> +int
> +ommmc_bus_width(sdmmc_chipset_handle_t sch, int width)
> +{
> + struct ommmc_softc *sc = sch;
> + int s;
> +
> + if (width != 1 && width != 4 && width != 8)
> + return (1);
> +
> + s = splsdmmc();
> +
> + if (width == 8)
> + HSET4(sc, MMCHS_CON, MMCHS_CON_DW8);
> + else
> + HCLR4(sc, MMCHS_CON, MMCHS_CON_DW8);
> +
> + if (width == 4)
> + HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);
> + else if (width == 1)
> + HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_DTW);
> +
> + splx(s);
> +
> + return (0);
> }
>
> void
>
