On Tue, Dec 01, 2015 at 04:51:24AM +0000, Scot Doyle wrote: > On Tue, 1 Dec 2015, Jonathan Gray wrote: > > On Tue, Dec 01, 2015 at 01:32:24AM +0000, Scot Doyle wrote: > > > from Todd Previte > > > Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices > > > 06ea66b6bb445043dc25a9626254d5c130093199 in mainline Linux > > > > > > refactored to only support the GPU's both capable of HBR2 and > > > currently supported by inteldrm: Broadwell and non-ULT Haswell > > > > > > ok? > > > > Could you describe what prompted you to look into this? A certain > > display wouldn't work otherwise? > > Yes, an Ultra HD monitor was refreshing at 30Hz with -current, and now > refreshes at 60. > > > Note that the check was a bit different before the code was overhauled > > again in later revisions. > > > > if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || > > INTEL_INFO(dev)->gen >= 8) && > > intel_dp->dpcd[DP_DPCD_REV] >= 0x12) > > > > ULX implies ULT but ULT doesn't imply ULX. > > After reviewing [1] I mistook support for UHD@60Hz with support for HBR2. > Thanks for pointing this out, ULX seems better. > > [1] > https://software.intel.com/en-us/articles/quick-reference-guide-to-intel-processor-graphics > > > I don't see the need for calling your hbr2_capable function under > > the "Training Pattern 3 support" section, why do that when > > the original code had a "intel_dp->dpcd[DP_DPCD_REV] >= 0x12" test? > > There was a report of dmesg clutter without the version check, when a > pre-Haswell gpu attached to a large (HBR2?) monitor in commit > 7809a61176b385ebb3299ea43c58b1bb31ffb8c0.
How about the following collection of commits then commit 06ea66b6bb445043dc25a9626254d5c130093199 Author: Todd Previte <[email protected]> Date: Mon Jan 20 10:19:39 2014 -0700 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices commit 9bbfd20abe5025adbb0ac75160bd2e41158a9e83 Author: Paulo Zanoni <[email protected]> Date: Tue Apr 29 11:00:22 2014 -0300 drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX commit f8d8a672f9370278ae2c9752ad3021662dbc42fd Author: Jani Nikula <[email protected]> Date: Fri Sep 5 16:19:18 2014 +0300 drm/i915/dp: add missing \n in the TPS3 debug message commit 7809a61176b385ebb3299ea43c58b1bb31ffb8c0 Author: Jani Nikula <[email protected]> Date: Wed Oct 29 11:03:26 2014 +0200 drm/i915/dp: only use training pattern 3 on platforms that support it Index: i915_pciids.h =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/i915_pciids.h,v retrieving revision 1.1 diff -u -p -r1.1 i915_pciids.h --- i915_pciids.h 23 Sep 2015 23:12:11 -0000 1.1 +++ i915_pciids.h 1 Dec 2015 05:33:06 -0000 @@ -192,8 +192,8 @@ INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ Index: i915/i915_drv.h =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/i915/i915_drv.h,v retrieving revision 1.72 diff -u -p -r1.72 i915_drv.h --- i915/i915_drv.h 1 Nov 2015 14:07:43 -0000 1.72 +++ i915/i915_drv.h 1 Dec 2015 05:32:13 -0000 @@ -1954,6 +1954,9 @@ struct drm_i915_file_private { #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ ((dev)->pdev->device & 0x00F0) == 0x0020) +/* ULX machines are also considered ULT. */ +#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ + (dev)->pdev->device == 0x0A1E) #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) /* Index: i915/intel_dp.c =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_dp.c,v retrieving revision 1.26 diff -u -p -r1.26 intel_dp.c --- i915/intel_dp.c 23 Sep 2015 23:12:12 -0000 1.26 +++ i915/intel_dp.c 1 Dec 2015 05:38:09 -0000 @@ -94,13 +94,19 @@ static int intel_dp_max_link_bw(struct intel_dp *intel_dp) { int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; + struct drm_device *dev = intel_dp->attached_connector->base.dev; switch (max_link_bw) { case DP_LINK_BW_1_62: case DP_LINK_BW_2_7: break; case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ - max_link_bw = DP_LINK_BW_2_7; + if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || + INTEL_INFO(dev)->gen >= 8) && + intel_dp->dpcd[DP_DPCD_REV] >= 0x12) + max_link_bw = DP_LINK_BW_5_4; + else + max_link_bw = DP_LINK_BW_2_7; break; default: WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", @@ -847,9 +853,10 @@ intel_dp_compute_config(struct intel_enc struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); - int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; + /* Conveniently, the link BW constants become indices with a shift...*/ + int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; int bpp, mode_rate; - static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; + static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; int link_avail, link_clock; if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) @@ -2673,10 +2680,15 @@ intel_dp_complete_link_train(struct inte bool channel_eq = false; int tries, cr_tries; uint32_t DP = intel_dp->DP; + uint32_t training_pattern = DP_TRAINING_PATTERN_2; + + /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ + if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) + training_pattern = DP_TRAINING_PATTERN_3; /* channel equalization */ if (!intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to start channel equalization\n"); return; @@ -2703,7 +2715,7 @@ intel_dp_complete_link_train(struct inte if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); cr_tries++; continue; @@ -2719,7 +2731,7 @@ intel_dp_complete_link_train(struct inte intel_dp_link_down(intel_dp); intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, - DP_TRAINING_PATTERN_2 | + training_pattern | DP_LINK_SCRAMBLING_DISABLE); tries = 0; cr_tries++; @@ -2864,6 +2876,15 @@ intel_dp_get_dpcd(struct intel_dp *intel DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); } } + + /* Training Pattern 3 support, both source and sink */ + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && + intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && + (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)) { + intel_dp->use_tps3 = true; + DRM_DEBUG_KMS("Displayport TPS3 supported\n"); + } else + intel_dp->use_tps3 = false; if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) Index: i915/intel_drv.h =================================================================== RCS file: /cvs/src/sys/dev/pci/drm/i915/intel_drv.h,v retrieving revision 1.8 diff -u -p -r1.8 intel_drv.h --- i915/intel_drv.h 23 Sep 2015 23:12:12 -0000 1.8 +++ i915/intel_drv.h 1 Dec 2015 05:31:47 -0000 @@ -497,6 +497,7 @@ struct intel_dp { struct delayed_work panel_vdd_work; bool want_panel_vdd; bool psr_setup_done; + bool use_tps3; struct intel_connector *attached_connector; };
