armv6 introduced dedicated instructions for enabling/disabling
interrupts. And while those don't easily map to to mask based
enable_interrupts/disable_interrupts macros, the following switches
some of the v7 only codepaths to use them.
The pmap_activate splhigh followed by disable_interrupts looks wrong,
but that is really another diff.
Index: arm/cpuswitch7.S
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/cpuswitch7.S,v
retrieving revision 1.3
diff -u -p -r1.3 cpuswitch7.S
--- arm/cpuswitch7.S 12 Sep 2013 11:43:51 -0000 1.3
+++ arm/cpuswitch7.S 28 Jan 2015 05:54:31 -0000
@@ -94,14 +94,10 @@
* XXX: This is not necessary if the vector table is relocated.
*/
#define IRQdisableALL \
- mrs r14, cpsr ; \
- orr r14, r14, #(I32_bit | F32_bit) ; \
- msr cpsr_c, r14
+ cpsid if
#define IRQenableALL \
- mrs r14, cpsr ; \
- bic r14, r14, #(I32_bit | F32_bit) ; \
- msr cpsr_c, r14
+ cpsie if
.text
Index: arm/pmap7.c
===================================================================
RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v
retrieving revision 1.18
diff -u -p -r1.18 pmap7.c
--- arm/pmap7.c 16 Nov 2014 12:30:56 -0000 1.18
+++ arm/pmap7.c 28 Jan 2015 05:54:33 -0000
@@ -2258,7 +2258,7 @@ pmap_activate(struct proc *p)
s = splhigh();
pmap_acquire_pmap_lock(pm);
- disable_interrupts(I32_bit | F32_bit);
+ __asm volatile("cpsid if");
/*
* We MUST, I repeat, MUST fix up the L1 entry corresponding
@@ -2278,7 +2278,7 @@ pmap_activate(struct proc *p)
cpu_domains(pcb->pcb_dacr);
cpu_setttb(pcb->pcb_pagedir);
- enable_interrupts(I32_bit | F32_bit);
+ __asm volatile("cpsie if");
pmap_release_pmap_lock(pm);
splx(s);
