On Wednesday 30 January 2013 3:49:34 am Mark Kettenis wrote:
> > Date: Tue, 29 Jan 2013 17:35:13 -0500
> > From: Matt Dainty <[email protected]>
> >
> > * Christian Weisgerber <[email protected]> [2013-01-24 13:03:43]:
> > > I think it's dubious that we match the CPU brand name for this at
> > > all. Shouldn't this be properly handled with CPUID?
> >
> > Here's a slightly simpler diff that checks the vendor rather than the
> > CPU brand.
> >
> > I'm not sure if it's safe to check CPUID regardless of vendor, plus
> > there is the CLFLUSH code in that block as well, I figure that's
> > confined to Intel for a reason?
>
> Look at the equivalent i386 code.
Looking at the the equivalent i386 code shows that ci_cflushsz is
only set when the vendor is Intel and the cpu features has CFLUSH
set. Also core update sensors are only checked when vendor is
Intel and cpuid_level >= 0x06. The following diff changes amd64
to follow these rules, allows the Atom E6XX sensors to attach and
brings amd64 closer to i386 for these items.
-Kurt
Index: sys/arch/amd64/amd64/identcpu.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v
retrieving revision 1.43
diff -u -p -r1.43 identcpu.c
--- sys/arch/amd64/amd64/identcpu.c 10 Nov 2012 09:45:05 -0000 1.43
+++ sys/arch/amd64/amd64/identcpu.c 12 Feb 2013 04:21:35 -0000
@@ -506,20 +506,24 @@ identifycpu(struct cpu_info *ci)
if (ci->ci_feature_sefflags & SEFF0EBX_SMAP)
replacesmap();
}
- if (!strncmp(mycpu_model, "Intel", 5)) {
- u_int32_t cflushsz;
+ if (!strcmp(cpu_vendor, "GenuineIntel")) {
+ if (ci->ci_feature_flags & CPUID_CFLUSH) {
+ u_int32_t cflushsz;
- CPUID(0x01, dummy, cflushsz, dummy, dummy);
- /* cflush cacheline size is equal to bits 15-8 of ebx * 8 */
- ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8;
- CPUID(0x06, val, dummy, dummy, dummy);
- if (val & 0x1) {
- strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
- sizeof(ci->ci_sensordev.xname));
- ci->ci_sensor.type = SENSOR_TEMP;
- sensor_task_register(ci, intelcore_update_sensor, 5);
- sensor_attach(&ci->ci_sensordev, &ci->ci_sensor);
- sensordev_install(&ci->ci_sensordev);
+ CPUID(0x01, dummy, cflushsz, dummy, dummy);
+ /* cflush cacheline size is equal to bits 15-8 of ebx *
8 */
+ ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8;
+ }
+ if (cpuid_level >= 0x06) {
+ CPUID(0x06, val, dummy, dummy, dummy);
+ if (val & 0x1) {
+ strlcpy(ci->ci_sensordev.xname,
ci->ci_dev->dv_xname,
+ sizeof(ci->ci_sensordev.xname));
+ ci->ci_sensor.type = SENSOR_TEMP;
+ sensor_task_register(ci,
intelcore_update_sensor, 5);
+ sensor_attach(&ci->ci_sensordev,
&ci->ci_sensor);
+ sensordev_install(&ci->ci_sensordev);
+ }
}
}