Le mer. 5 déc. 2018 à 08:39, Masanobu SAITOH <[email protected]> a écrit : > I suspect Serial ATA AHCI 1.2.1 specification page 111 has the hint. > > Figure 23: Port/CCC and MSI Message Mapping, Example 1 > Figure 24: Port and MSI Message Mapping, Example 2 > > I suspect MSI-X also assume this layout. pci_msix_alloc_map() might > be used.
Very likely we need to disable MSICAP.MME bit if MSI happens to have more vectors to force single MSI operation. There is no such bit for MSI-X. Let's work on this off-list, I have some idea to test the interrupt mapping, and actually add support for multiple vectors. Since in your case the thing only fails for IDENTIFY, it looks like the registers mapped via regular BAR work and just interrupt routing is bad. Performance wise it doesn't buy much besides avoiding one register read per interrupt, because the whole ATA subsystem is not MPSAFE and hence the interrupt handlers are serialized via KERNEL_LOCK() anyway. > My SuperMicro A2SDi-H-TP4F's disk is connected to not channel 0 > but channel 6. I also verified that GHC.MRSM is 0. GHC.MRSM is only set if hardware has less MSI/MSI-X vectors than AHCI ports, and fallbacks to single MSI due to this. So it's actually normal for this to be 0. It'd be quite strange for hardware to have less MSI/MSI-X vectors than supported ports. Jaromir
