On Mon, Aug 31, 2015 at 03:01:19PM +0200, Stephan wrote:
> Ok thanks, so it´s based on software. Couldn´t this potentially be
> implemented in hardware, as long as the particular architecture
> supports it (that´s how I understand the APIC´s task priority register
> on x86)?
For x86 I don't know. Shared interrupt lines may make it difficult.
I did a full-hardware implementation of the spl framework for mips,
on a custom board: I use the CPU's interrupt masks as spl levels, and
the hardware can route any peripheral interrupt to any CPU IRQ line.
This solves the interrup sharing problem by routing all interrupts with
the same spl level to the same CPU line. Of course for this to work the
harware has to allow arbitrary interrupt routing.
--
Manuel Bouyer <bou...@antioche.eu.org>
NetBSD: 26 ans d'experience feront toujours la difference
--
