Author: dim
Date: Tue Sep 5 17:35:33 2017
New Revision: 323190
URL: https://svnweb.freebsd.org/changeset/base/323190
Log:
MFC r323001:
In compiler-rt, a few assembler implementations for i386 floating point
conversion functions use SSE2 instructions, but these are not guarded by
#ifdef __SSE2__, and there is no implementation using general purpose
registers. For these functions, use the generic C variants instead,
otherwise they will cause SIGILL on older processors.
Reported by: bs...@phoe.frmug.org
PR: 221733
MFC r323014:
Follow-up to r323001: if the actually selected CPUTYPE is capable of
SSE2 instructions, we can use them.
Suggested by: jkim
Modified:
stable/9/lib/libcompiler_rt/Makefile
Directory Properties:
stable/9/ (props changed)
stable/9/lib/ (props changed)
stable/9/lib/libcompiler_rt/ (props changed)
Modified: stable/9/lib/libcompiler_rt/Makefile
==============================================================================
--- stable/9/lib/libcompiler_rt/Makefile Tue Sep 5 17:32:14 2017
(r323189)
+++ stable/9/lib/libcompiler_rt/Makefile Tue Sep 5 17:35:33 2017
(r323190)
@@ -65,15 +65,9 @@ SRCF= absvdi2 \
fixunsxfti \
fixxfdi \
fixxfti \
- floatdidf \
- floatdisf \
- floatdixf \
floattidf \
floattisf \
floattixf \
- floatundidf \
- floatundisf \
- floatundixf \
floatunsidf \
floatunsisf \
floatuntidf \
@@ -125,6 +119,23 @@ SRCF= absvdi2 \
udivti3 \
umoddi3 \
umodti3
+
+# Avoid using SSE2 instructions on i386, if unsupported.
+.if ${MACHINE_CPUARCH} == "i386" && empty(MACHINE_CPU:Msse2)
+SRCS+= floatdidf.c
+SRCS+= floatdisf.c
+SRCS+= floatdixf.c
+SRCS+= floatundidf.c
+SRCS+= floatundisf.c
+SRCS+= floatundixf.c
+.else
+SRCF+= floatdidf
+SRCF+= floatdisf
+SRCF+= floatdixf
+SRCF+= floatundidf
+SRCF+= floatundisf
+SRCF+= floatundixf
+.endif
# These are already shipped by libc.a on arm and mips
.if ${MACHINE_CPUARCH} != "arm" && ${MACHINE_CPUARCH} != "mips"
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