Author: kib
Date: Tue Dec 4 00:51:29 2012
New Revision: 243848
URL: http://svnweb.freebsd.org/changeset/base/243848
Log:
MFC r242433:
Enable the new instructions for reading and writing bases for %fs,
%gs, when supported. Enable SMEP when supported.
MFC r242828:
Do not try to enable new features in the %cr4 if running under hypervisor.
Modified:
stable/9/sys/amd64/amd64/identcpu.c
stable/9/sys/amd64/amd64/initcpu.c
stable/9/sys/amd64/amd64/pmap.c
Directory Properties:
stable/9/sys/ (props changed)
Modified: stable/9/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/9/sys/amd64/amd64/identcpu.c Tue Dec 4 00:44:31 2012
(r243847)
+++ stable/9/sys/amd64/amd64/identcpu.c Tue Dec 4 00:51:29 2012
(r243848)
@@ -481,7 +481,7 @@ SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE,
void
identify_cpu(void)
{
- u_int regs[4];
+ u_int regs[4], cpu_stdext_disable;
do_cpuid(0, regs);
cpu_high = regs[0];
@@ -516,6 +516,20 @@ identify_cpu(void)
if (cpu_high >= 7) {
cpuid_count(7, 0, regs);
cpu_stdext_feature = regs[1];
+
+ /*
+ * Some hypervisors fail to filter out unsupported
+ * extended features. For now, disable the
+ * extensions, activation of which requires setting a
+ * bit in CR4, and which VM monitors do not support.
+ */
+ if (cpu_feature2 & CPUID2_HV) {
+ cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
+ CPUID_STDEXT_SMEP;
+ } else
+ cpu_stdext_disable = 0;
+ TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
+ cpu_stdext_feature &= ~cpu_stdext_disable;
}
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
Modified: stable/9/sys/amd64/amd64/initcpu.c
==============================================================================
--- stable/9/sys/amd64/amd64/initcpu.c Tue Dec 4 00:44:31 2012
(r243847)
+++ stable/9/sys/amd64/amd64/initcpu.c Tue Dec 4 00:51:29 2012
(r243848)
@@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/kernel.h>
+#include <sys/pcpu.h>
#include <sys/systm.h>
#include <sys/sysctl.h>
@@ -153,11 +154,25 @@ void
initializecpu(void)
{
uint64_t msr;
+ uint32_t cr4;
+ cr4 = rcr4();
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
- load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
+ cr4 |= CR4_FXSR | CR4_XMM;
cpu_fxsr = hw_instruction_sse = 1;
}
+ if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
+ cr4 |= CR4_FSGSBASE;
+
+ /*
+ * Postpone enabling the SMEP on the boot CPU until the page
+ * tables are switched from the boot loader identity mapping
+ * to the kernel tables. The boot loader enables the U bit in
+ * its tables.
+ */
+ if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
+ cr4 |= CR4_SMEP;
+ load_cr4(cr4);
if ((amd_feature & AMDID_NX) != 0) {
msr = rdmsr(MSR_EFER) | EFER_NXE;
wrmsr(MSR_EFER, msr);
Modified: stable/9/sys/amd64/amd64/pmap.c
==============================================================================
--- stable/9/sys/amd64/amd64/pmap.c Tue Dec 4 00:44:31 2012
(r243847)
+++ stable/9/sys/amd64/amd64/pmap.c Tue Dec 4 00:51:29 2012
(r243848)
@@ -629,6 +629,8 @@ pmap_bootstrap(vm_paddr_t *firstaddr)
/* XXX do %cr0 as well */
load_cr4(rcr4() | CR4_PGE | CR4_PSE);
load_cr3(KPML4phys);
+ if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
+ load_cr4(rcr4() | CR4_SMEP);
/*
* Initialize the kernel pmap (which is statically allocated).
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