Author: kevans
Date: Thu Jun 14 18:34:02 2018
New Revision: 335168
URL: https://svnweb.freebsd.org/changeset/base/335168
Log:
a10_ahci: Correct clock indices for new bindings
r329104 imported 4.15 DTS which brought CCU to a10/a20. In the process, they
swapped the ordering of 'clocks' for allwinner,sun4i-a10-ahci on both
sun4i-a10 and sun7i-a20 from PLL, Gate to Gate, PLL.
Swap it in the driver.
Modified:
head/sys/arm/allwinner/a10_ahci.c
Modified: head/sys/arm/allwinner/a10_ahci.c
==============================================================================
--- head/sys/arm/allwinner/a10_ahci.c Thu Jun 14 18:33:09 2018
(r335167)
+++ head/sys/arm/allwinner/a10_ahci.c Thu Jun 14 18:34:02 2018
(r335168)
@@ -313,14 +313,14 @@ ahci_a10_attach(device_t dev)
return (ENXIO);
/* Enable clocks */
- error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll);
+ error = clk_get_by_ofw_index(dev, 0, 0, &clk_gate);
if (error != 0) {
- device_printf(dev, "Cannot get PLL clock\n");
+ device_printf(dev, "Cannot get gate clock\n");
goto fail;
}
- error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate);
+ error = clk_get_by_ofw_index(dev, 0, 1, &clk_pll);
if (error != 0) {
- device_printf(dev, "Cannot get gate clock\n");
+ device_printf(dev, "Cannot get PLL clock\n");
goto fail;
}
error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
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