Author: manu
Date: Tue Jun 12 11:47:21 2018
New Revision: 334996
URL: https://svnweb.freebsd.org/changeset/base/334996
Log:
arm64: rockchip: Correctly set armclk
Parent needs to be the same frequency as the armclk, not twice the freq.
The real divider is incremented by one so write it with - 1
The rate can be at index 0
Pointy Hat To: myself
Modified:
head/sys/arm64/rockchip/clk/rk_clk_armclk.c
Modified: head/sys/arm64/rockchip/clk/rk_clk_armclk.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_armclk.c Tue Jun 12 10:43:20 2018
(r334995)
+++ head/sys/arm64/rockchip/clk/rk_clk_armclk.c Tue Jun 12 11:47:21 2018
(r334996)
@@ -154,12 +154,13 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t f
if (sc->rates[i].freq == *fout) {
best = sc->rates[i].freq;
div = sc->rates[i].div;
- best_p = best * (div + 1);
+ best_p = best * div;
rate = i;
+ break;
}
}
- if (rate == 0)
+ if (rate == sc->nrates)
return (0);
err = clknode_set_freq(p_main, best_p, 0, 1);
@@ -177,7 +178,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t f
DEVICE_LOCK(clk);
READ4(clk, sc->muxdiv_offset, &val);
val &= ~sc->div_mask;
- val |= div << sc->div_shift;
+ val |= (div - 1) << sc->div_shift;
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_ARMCLK_MASK);
DEVICE_UNLOCK(clk);
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