Author: manu
Date: Mon May 7 07:28:47 2018
New Revision: 333316
URL: https://svnweb.freebsd.org/changeset/base/333316
Log:
arm64: rk3328: Add pll rates tables
Add the known value to be safe for the rk3328 PLLs
Modified:
head/sys/arm64/rockchip/clk/rk3328_cru.c
Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk3328_cru.c Mon May 7 07:28:10 2018
(r333315)
+++ head/sys/arm64/rockchip/clk/rk3328_cru.c Mon May 7 07:28:47 2018
(r333316)
@@ -103,6 +103,404 @@ static struct rk_cru_gate rk3328_gates[] = {
#define PLL_GPLL 4
#define PLL_NPLL 5
+static struct rk_clk_pll_rate rk3328_pll_rates[] = {
+ {
+ .freq = 1608000000,
+ .refdiv = 1,
+ .fbdiv = 67,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1584000000,
+ .refdiv = 1,
+ .fbdiv = 66,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1560000000,
+ .refdiv = 1,
+ .fbdiv = 65,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1536000000,
+ .refdiv = 1,
+ .fbdiv = 64,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1512000000,
+ .refdiv = 1,
+ .fbdiv = 63,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1488000000,
+ .refdiv = 1,
+ .fbdiv = 62,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1464000000,
+ .refdiv = 1,
+ .fbdiv = 61,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1440000000,
+ .refdiv = 1,
+ .fbdiv = 60,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1416000000,
+ .refdiv = 1,
+ .fbdiv = 59,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1392000000,
+ .refdiv = 1,
+ .fbdiv = 58,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1368000000,
+ .refdiv = 1,
+ .fbdiv = 57,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1344000000,
+ .refdiv = 1,
+ .fbdiv = 56,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1320000000,
+ .refdiv = 1,
+ .fbdiv = 55,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1296000000,
+ .refdiv = 1,
+ .fbdiv = 54,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1272000000,
+ .refdiv = 1,
+ .fbdiv = 53,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1248000000,
+ .refdiv = 1,
+ .fbdiv = 52,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1200000000,
+ .refdiv = 1,
+ .fbdiv = 50,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1188000000,
+ .refdiv = 2,
+ .fbdiv = 99,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1104000000,
+ .refdiv = 1,
+ .fbdiv = 46,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1100000000,
+ .refdiv = 12,
+ .fbdiv = 550,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1008000000,
+ .refdiv = 1,
+ .fbdiv = 84,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 1000000000,
+ .refdiv = 6,
+ .fbdiv = 500,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 984000000,
+ .refdiv = 1,
+ .fbdiv = 82,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 960000000,
+ .refdiv = 1,
+ .fbdiv = 80,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 936000000,
+ .refdiv = 1,
+ .fbdiv = 78,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 912000000,
+ .refdiv = 1,
+ .fbdiv = 76,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 900000000,
+ .refdiv = 4,
+ .fbdiv = 300,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 888000000,
+ .refdiv = 1,
+ .fbdiv = 74,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 864000000,
+ .refdiv = 1,
+ .fbdiv = 72,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 840000000,
+ .refdiv = 1,
+ .fbdiv = 70,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 816000000,
+ .refdiv = 1,
+ .fbdiv = 68,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 800000000,
+ .refdiv = 6,
+ .fbdiv = 400,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 700000000,
+ .refdiv = 6,
+ .fbdiv = 350,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 696000000,
+ .refdiv = 1,
+ .fbdiv = 58,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 600000000,
+ .refdiv = 1,
+ .fbdiv = 75,
+ .postdiv1 = 3,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 594000000,
+ .refdiv = 2,
+ .fbdiv = 99,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 504000000,
+ .refdiv = 1,
+ .fbdiv = 63,
+ .postdiv1 = 3,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 500000000,
+ .refdiv = 6,
+ .fbdiv = 250,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 408000000,
+ .refdiv = 1,
+ .fbdiv = 68,
+ .postdiv1 = 2,
+ .postdiv2 = 2,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 312000000,
+ .refdiv = 1,
+ .fbdiv = 52,
+ .postdiv1 = 2,
+ .postdiv2 = 2,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 216000000,
+ .refdiv = 1,
+ .fbdiv = 72,
+ .postdiv1 = 4,
+ .postdiv2 = 2,
+ .dsmpd = 1,
+ },
+ {
+ .freq = 96000000,
+ .refdiv = 1,
+ .fbdiv = 64,
+ .postdiv1 = 4,
+ .postdiv2 = 4,
+ .dsmpd = 1,
+ },
+ {},
+};
+
+static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = {
+ {
+ .freq = 1016064000,
+ .refdiv = 3,
+ .fbdiv = 127,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 0,
+ .frac = 134217,
+ },
+ {
+ .freq = 983040000,
+ .refdiv = 24,
+ .fbdiv = 983,
+ .postdiv1 = 1,
+ .postdiv2 = 1,
+ .dsmpd = 0,
+ .frac = 671088,
+ },
+ {
+ .freq = 491520000,
+ .refdiv = 24,
+ .fbdiv = 983,
+ .postdiv1 = 2,
+ .postdiv2 = 1,
+ .dsmpd = 0,
+ .frac = 671088,
+ },
+ {
+ .freq = 61440000,
+ .refdiv = 6,
+ .fbdiv = 215,
+ .postdiv1 = 7,
+ .postdiv2 = 2,
+ .dsmpd = 0,
+ .frac = 671088,
+ },
+ {
+ .freq = 56448000,
+ .refdiv = 12,
+ .fbdiv = 451,
+ .postdiv1 = 4,
+ .postdiv2 = 4,
+ .dsmpd = 0,
+ .frac = 9797894,
+ },
+ {
+ .freq = 40960000,
+ .refdiv = 12,
+ .fbdiv = 409,
+ .postdiv1 = 4,
+ .postdiv2 = 5,
+ .dsmpd = 0,
+ .frac = 10066329,
+ },
+ {},
+};
+
static const char *pll_parents[] = {"xin24m"};
static struct rk_clk_pll_def apll = {
.clkdef = {
@@ -115,6 +513,7 @@ static struct rk_clk_pll_def apll = {
.gate_offset = 0x200,
.gate_shift = 0,
.flags = RK_CLK_PLL_HAVE_GATE,
+ .frac_rates = rk3328_pll_frac_rates,
};
static struct rk_clk_pll_def dpll = {
@@ -138,6 +537,7 @@ static struct rk_clk_pll_def cpll = {
.parent_cnt = nitems(pll_parents),
},
.base_offset = 0x40,
+ .rates = rk3328_pll_rates,
};
static struct rk_clk_pll_def gpll = {
@@ -151,6 +551,7 @@ static struct rk_clk_pll_def gpll = {
.gate_offset = 0x200,
.gate_shift = 2,
.flags = RK_CLK_PLL_HAVE_GATE,
+ .frac_rates = rk3328_pll_frac_rates,
};
static struct rk_clk_pll_def npll = {
@@ -164,6 +565,7 @@ static struct rk_clk_pll_def npll = {
.gate_offset = 0x200,
.gate_shift = 12,
.flags = RK_CLK_PLL_HAVE_GATE,
+ .rates = rk3328_pll_rates,
};
/* CRU_CLKSEL_CON0 */
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