Author: br
Date: Mon Apr 23 12:23:05 2018
New Revision: 332887
URL: https://svnweb.freebsd.org/changeset/base/332887
Log:
Enable ARM PL330 DMA engine and Cadence Quad SPI flash controller on
Intel Arria 10 SoC boards.
Tested on Intel Arria 10 SoC Development Kit.
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm/conf/SOCFPGA
head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts
Modified: head/sys/arm/conf/SOCFPGA
==============================================================================
--- head/sys/arm/conf/SOCFPGA Mon Apr 23 12:20:07 2018 (r332886)
+++ head/sys/arm/conf/SOCFPGA Mon Apr 23 12:23:05 2018 (r332887)
@@ -47,6 +47,10 @@ options INTRNG
# ARM MPCore timer
device mpcore_timer
+# DMA support
+device xdma
+device pl330
+
# MMC/SD/SDIO Card slot support
device mmc # mmc/sd bus
device mmcsd # mmc/sd flash cards
@@ -80,6 +84,8 @@ device iicbus
# SPI
device spibus
+device cqspi
+device n25q
# Ethernet
device ether
Modified: head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts
==============================================================================
--- head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts Mon Apr 23 12:20:07
2018 (r332886)
+++ head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts Mon Apr 23 12:23:05
2018 (r332887)
@@ -84,3 +84,37 @@
&usb0 {
dr_mode = "host";
};
+
+&qspi {
+ status = "okay";
+
+ dmas = <&pdma 24>, <&pdma 25>;
+ dma-names = "tx", "rx";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00aa";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@qspi-boot {
+ label = "boot";
+ reg = <0x0 0x2720000>;
+ };
+
+ partition@qspi-rootfs {
+ label = "rootfs";
+ reg = <0x2720000 0x58E0000>;
+ };
+ };
+};
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