Author: wma
Date: Fri Jan 12 12:14:52 2018
New Revision: 327873
URL: https://svnweb.freebsd.org/changeset/base/327873
Log:
PowerNV: update OPAL driver
Update OPAL driver with:
- better console support
- proper AP configuration
- enhanced IRQ/OFW mapping
- RTC support
Created by: Nathan Whitehorn <nwhiteh...@freebsd.org>
Submitted by: Wojciech Macek <w...@semihalf.com>
Sponsored by: FreeBSD Foundation
Modified:
head/sys/powerpc/powernv/opal.h
head/sys/powerpc/powernv/opal_console.c
head/sys/powerpc/powernv/opal_dev.c
head/sys/powerpc/powernv/platform_powernv.c
Modified: head/sys/powerpc/powernv/opal.h
==============================================================================
--- head/sys/powerpc/powernv/opal.h Fri Jan 12 12:14:14 2018
(r327872)
+++ head/sys/powerpc/powernv/opal.h Fri Jan 12 12:14:52 2018
(r327873)
@@ -40,9 +40,12 @@ int opal_call(uint64_t token, ...);
#define OPAL_CONSOLE_WRITE 1
#define OPAL_CONSOLE_READ 2
+#define OPAL_RTC_READ 3
+#define OPAL_RTC_WRITE 4
#define OPAL_CEC_POWER_DOWN 5
#define OPAL_CEC_REBOOT 6
#define OPAL_HANDLE_INTERRUPT 9
+#define OPAL_POLL_EVENTS 10
#define OPAL_PCI_CONFIG_READ_BYTE 13
#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
#define OPAL_PCI_CONFIG_READ_WORD 15
@@ -57,10 +60,10 @@ int opal_call(uint64_t token, ...);
#define OPAL_PCI_RESET 49
#define OPAL_PCI_POLL 62
#define OPAL_PCI_SET_PE 31
-#define OPAL_START_CPU 41
#define OPAL_GET_MSI_32 39
#define OPAL_GET_MSI_64 40
#define OPAL_PCI_MSI_EOI 63
+#define OPAL_START_CPU 41
#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
#define OPAL_RETURN_CPU 69
#define OPAL_REINIT_CPUS 70
Modified: head/sys/powerpc/powernv/opal_console.c
==============================================================================
--- head/sys/powerpc/powernv/opal_console.c Fri Jan 12 12:14:14 2018
(r327872)
+++ head/sys/powerpc/powernv/opal_console.c Fri Jan 12 12:14:52 2018
(r327873)
@@ -133,42 +133,39 @@ static struct {
char tmpbuf[16];
uint64_t size;
struct mtx mtx;
-} escapehatch;
+} opalcons_buffer;
static void
uart_opal_real_map_outbuffer(uint64_t *bufferp, uint64_t *lenp)
{
- if (!mtx_initialized(&escapehatch.mtx))
- mtx_init(&escapehatch.mtx, "uart_opal", NULL, MTX_SPIN |
MTX_QUIET |
- MTX_NOWITNESS);
+ if (!mtx_initialized(&opalcons_buffer.mtx))
+ mtx_init(&opalcons_buffer.mtx, "uart_opal", NULL,
+ MTX_SPIN | MTX_QUIET | MTX_NOWITNESS);
if (!pmap_bootstrapped)
return;
- if (TD_IS_IDLETHREAD(curthread)) {
- escapehatch.size = *(uint64_t *)(*lenp) =
- min(sizeof(escapehatch.tmpbuf), *(uint64_t *)(*lenp));
- mtx_lock_spin(&escapehatch.mtx);
- memcpy(escapehatch.tmpbuf, (void *)(*bufferp), *(uint64_t
*)(*lenp));
- *bufferp = (uint64_t)escapehatch.tmpbuf;
- *lenp = (uint64_t)&escapehatch.size;
- }
+ mtx_lock_spin(&opalcons_buffer.mtx);
- *bufferp = vtophys(*bufferp);
- *lenp = vtophys(*lenp);
+ opalcons_buffer.size = *(uint64_t *)(*lenp) =
+ min(sizeof(opalcons_buffer.tmpbuf), *(uint64_t *)(*lenp));
+ memcpy(opalcons_buffer.tmpbuf, (void *)(*bufferp),
+ *(uint64_t *)(*lenp));
+ *bufferp = (uint64_t)opalcons_buffer.tmpbuf;
+ *lenp = (uint64_t)&opalcons_buffer.size;
}
static void
-uart_opal_real_unmap_outbuffer(uint64_t lenp, uint64_t *origlen)
+uart_opal_real_unmap_outbuffer(uint64_t *len)
{
- if (!pmap_bootstrapped || !TD_IS_IDLETHREAD(curthread))
+ if (!pmap_bootstrapped)
return;
- mtx_assert(&escapehatch.mtx, MA_OWNED);
- *origlen = escapehatch.size;
- mtx_unlock_spin(&escapehatch.mtx);
+ mtx_assert(&opalcons_buffer.mtx, MA_OWNED);
+ *len = opalcons_buffer.size;
+ mtx_unlock_spin(&opalcons_buffer.mtx);
}
static int
@@ -187,7 +184,7 @@ uart_opal_probe_node(struct uart_opal_softc *sc)
return (ENXIO);
reg = -1;
- OF_getprop(node, "reg", ®, sizeof(reg));
+ OF_getencprop(node, "reg", ®, sizeof(reg));
if (reg == -1)
return (ENXIO);
sc->vtermid = reg;
@@ -389,7 +386,7 @@ uart_opal_put(struct uart_opal_softc *sc, void *buffer
uart_opal_real_map_outbuffer(&obuf, &olen);
err = opal_call(OPAL_CONSOLE_WRITE, sc->vtermid, olen, obuf);
- uart_opal_real_unmap_outbuffer(olen, &len);
+ uart_opal_real_unmap_outbuffer(&len);
} else {
uart_lock(&sc->sc_mtx);
if (bufsize > 12)
@@ -404,7 +401,7 @@ uart_opal_put(struct uart_opal_softc *sc, void *buffer
uart_opal_real_map_outbuffer(&obuf, &olen);
err = opal_call(OPAL_CONSOLE_WRITE, sc->vtermid, olen, obuf);
- uart_opal_real_unmap_outbuffer(olen, &len);
+ uart_opal_real_unmap_outbuffer(&len);
uart_unlock(&sc->sc_mtx);
@@ -438,7 +435,11 @@ uart_opal_cngetc(struct consdev *cp)
static void
uart_opal_cnputc(struct consdev *cp, int c)
{
+ static uint64_t events;
unsigned char ch = c;
+
+ if (cold)
+ opal_call(OPAL_POLL_EVENTS, &events); /* Clear FIFO if needed */
uart_opal_put(console_sc, &ch, 1);
}
Modified: head/sys/powerpc/powernv/opal_dev.c
==============================================================================
--- head/sys/powerpc/powernv/opal_dev.c Fri Jan 12 12:14:14 2018
(r327872)
+++ head/sys/powerpc/powernv/opal_dev.c Fri Jan 12 12:14:52 2018
(r327873)
@@ -37,7 +37,11 @@ __FBSDID("$FreeBSD$");
#include <sys/kernel.h>
#include <sys/reboot.h>
#include <sys/sysctl.h>
+#include <sys/endian.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/ofw/openfirm.h>
@@ -55,6 +59,7 @@ static const struct ofw_bus_devinfo *opaldev_get_devin
device_t child);
static void opal_shutdown(void *arg, int howto);
+static void opal_intr(void *);
static device_method_t opaldev_methods[] = {
/* Device interface */
@@ -89,6 +94,9 @@ DRIVER_MODULE(opaldev, ofwbus, opaldev_driver, opaldev
static int
opaldev_probe(device_t dev)
{
+ phandle_t iparent;
+ pcell_t *irqs;
+ int i, n_irqs;
if (!ofw_bus_is_compatible(dev, "ibm,opal-v3"))
return (ENXIO);
@@ -96,6 +104,24 @@ opaldev_probe(device_t dev)
return (ENXIO);
device_set_desc(dev, "OPAL Abstraction Firmware");
+
+ /* Manually add IRQs before attaching */
+ if (OF_hasprop(ofw_bus_get_node(dev), "opal-interrupts")) {
+ iparent = OF_finddevice("/interrupt-controller@0");
+ iparent = OF_xref_from_node(iparent);
+
+ n_irqs = OF_getproplen(ofw_bus_get_node(dev),
+ "opal-interrupts") / sizeof(*irqs);
+ irqs = malloc(n_irqs * sizeof(*irqs), M_DEVBUF, M_WAITOK);
+ OF_getencprop(ofw_bus_get_node(dev), "opal-interrupts", irqs,
+ n_irqs * sizeof(*irqs));
+ for (i = 0; i < n_irqs; i++)
+ bus_set_resource(dev, SYS_RES_IRQ, i,
+ ofw_bus_map_intr(dev, iparent, 1, &irqs[i]), 1);
+ free(irqs, M_DEVBUF);
+ }
+
+
return (BUS_PROBE_SPECIFIC);
}
@@ -104,14 +130,32 @@ opaldev_attach(device_t dev)
{
phandle_t child;
device_t cdev;
+ uint64_t junk;
+ int i, rv;
struct ofw_bus_devinfo *dinfo;
+ struct resource *irq;
- if (0 /* XXX NOT YET TEST FOR RTC */)
+ /* Test for RTC support and register clock if it works */
+ rv = opal_call(OPAL_RTC_READ, vtophys(&junk), vtophys(&junk));
+ do {
+ rv = opal_call(OPAL_RTC_READ, vtophys(&junk), vtophys(&junk));
+ if (rv == OPAL_BUSY_EVENT)
+ rv = opal_call(OPAL_POLL_EVENTS, 0);
+ } while (rv == OPAL_BUSY_EVENT);
+
+ if (rv == OPAL_SUCCESS)
clock_register(dev, 2000);
EVENTHANDLER_REGISTER(shutdown_final, opal_shutdown, NULL,
SHUTDOWN_PRI_LAST);
+ /* Bind to interrupts */
+ for (i = 0; (irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
+ RF_ACTIVE)) != NULL; i++)
+ bus_setup_intr(dev, irq, INTR_TYPE_TTY | INTR_MPSAFE |
+ INTR_ENTROPY, NULL, opal_intr, (void *)rman_get_start(irq),
+ NULL);
+
for (child = OF_child(ofw_bus_get_node(dev)); child != 0;
child = OF_peer(child)) {
dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO);
@@ -134,13 +178,56 @@ opaldev_attach(device_t dev)
}
static int
-opal_gettime(device_t dev, struct timespec *ts) {
- return (ENXIO);
+bcd2bin32(int bcd)
+{
+ int out = 0;
+
+ out += bcd2bin(bcd & 0xff);
+ out += 100*bcd2bin((bcd & 0x0000ff00) >> 8);
+ out += 10000*bcd2bin((bcd & 0x00ff0000) >> 16);
+ out += 1000000*bcd2bin((bcd & 0xffff0000) >> 24);
+
+ return (out);
}
static int
+opal_gettime(device_t dev, struct timespec *ts)
+{
+ int rv;
+ struct clocktime ct;
+ uint32_t ymd;
+ uint64_t hmsm;
+
+ do {
+ rv = opal_call(OPAL_RTC_READ, vtophys(&ymd), vtophys(&hmsm));
+ if (rv == OPAL_BUSY_EVENT) {
+ rv = opal_call(OPAL_POLL_EVENTS, 0);
+ pause("opalrtc", 1);
+ }
+ } while (rv == OPAL_BUSY_EVENT);
+
+ if (rv != OPAL_SUCCESS)
+ return (ENXIO);
+
+ hmsm = be64toh(hmsm);
+ ymd = be32toh(ymd);
+
+ ct.nsec = bcd2bin32((hmsm & 0x000000ffffff0000) >> 16) * 1000;
+ ct.sec = bcd2bin((hmsm & 0x0000ff0000000000) >> 40);
+ ct.min = bcd2bin((hmsm & 0x00ff000000000000) >> 48);
+ ct.hour = bcd2bin((hmsm & 0xff00000000000000) >> 56);
+
+ ct.day = bcd2bin((ymd & 0x000000ff) >> 0);
+ ct.mon = bcd2bin((ymd & 0x0000ff00) >> 8);
+ ct.year = bcd2bin32((ymd & 0xffff0000) >> 16);
+
+ return (clock_ct_to_ts(&ct, ts));
+}
+
+static int
opal_settime(device_t dev, struct timespec *ts)
{
+
return (0);
}
@@ -158,5 +245,18 @@ opal_shutdown(void *arg, int howto)
opal_call(OPAL_CEC_POWER_DOWN, 0 /* Normal power off */);
else
opal_call(OPAL_CEC_REBOOT);
+
+ opal_call(OPAL_RETURN_CPU);
+}
+
+static void
+opal_intr(void *xintr)
+{
+ uint64_t events = 0;
+
+ opal_call(OPAL_HANDLE_INTERRUPT, (uint32_t)(uint64_t)xintr,
+ vtophys(&events));
+ /* XXX: do something useful with this information */
+
}
Modified: head/sys/powerpc/powernv/platform_powernv.c
==============================================================================
--- head/sys/powerpc/powernv/platform_powernv.c Fri Jan 12 12:14:14 2018
(r327872)
+++ head/sys/powerpc/powernv/platform_powernv.c Fri Jan 12 12:14:52 2018
(r327873)
@@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/openfirm.h>
#include <machine/ofw_machdep.h>
+#include <powerpc/aim/mmu_oea64.h>
#include "platform_if.h"
#include "opal.h"
@@ -101,6 +102,8 @@ static platform_def_t powernv_platform = {
PLATFORM_DEF(powernv_platform);
+static int powernv_boot_pir;
+
static int
powernv_probe(platform_t plat)
{
@@ -113,17 +116,98 @@ powernv_probe(platform_t plat)
static int
powernv_attach(platform_t plat)
{
+ uint32_t nptlp, shift = 0, slb_encoding = 0;
+ int32_t lp_size, lp_encoding;
+ char buf[255];
+ pcell_t prop;
+ phandle_t cpu;
+ int res, len, node, idx;
+
/* Ping OPAL again just to make sure */
opal_check();
cpu_idle_hook = powernv_cpu_idle;
+ powernv_boot_pir = mfspr(SPR_PIR);
- /* Direct interrupts to SRR instead of HSRR */
- mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_LPES);
+ /* Init CPU bits */
+ powernv_smp_ap_init(plat);
+ /* Set SLB count from device tree */
+ cpu = OF_peer(0);
+ cpu = OF_child(cpu);
+ while (cpu != 0) {
+ res = OF_getprop(cpu, "name", buf, sizeof(buf));
+ if (res > 0 && strcmp(buf, "cpus") == 0)
+ break;
+ cpu = OF_peer(cpu);
+ }
+ if (cpu == 0)
+ goto out;
+
+ cpu = OF_child(cpu);
+ while (cpu != 0) {
+ res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
+ if (res > 0 && strcmp(buf, "cpu") == 0)
+ break;
+ cpu = OF_peer(cpu);
+ }
+ if (cpu == 0)
+ goto out;
+
+ res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop));
+ if (res > 0)
+ n_slbs = prop;
+
+ /*
+ * Scan the large page size property for PAPR compatible machines.
+ * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties'
+ * for the encoding of the property.
+ */
+
+ len = OF_getproplen(node, "ibm,segment-page-sizes");
+ if (len > 0) {
+ /*
+ * We have to use a variable length array on the stack
+ * since we have very limited stack space.
+ */
+ pcell_t arr[len/sizeof(cell_t)];
+ res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr,
+ sizeof(arr));
+ len /= 4;
+ idx = 0;
+ while (len > 0) {
+ shift = arr[idx];
+ slb_encoding = arr[idx + 1];
+ nptlp = arr[idx + 2];
+ idx += 3;
+ len -= 3;
+ while (len > 0 && nptlp) {
+ lp_size = arr[idx];
+ lp_encoding = arr[idx+1];
+ if (slb_encoding == SLBV_L && lp_encoding == 0)
+ break;
+
+ idx += 2;
+ len -= 2;
+ nptlp--;
+ }
+ if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0)
+ break;
+ }
+
+ if (len == 0)
+ panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) "
+ "not supported by this system.");
+
+ moea64_large_page_shift = shift;
+ moea64_large_page_size = 1ULL << lp_size;
+ }
+
+out:
return (0);
}
+
void
powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
struct mem_region *avail, int *availsz)
@@ -140,7 +224,7 @@ powernv_timebase_freq(platform_t plat, struct cpuref *
phandle = cpuref->cr_hwref;
- OF_getprop(phandle, "timebase-frequency", &ticks, sizeof(ticks));
+ OF_getencprop(phandle, "timebase-frequency", &ticks, sizeof(ticks));
if (ticks <= 0)
panic("Unable to determine timebase frequency!");
@@ -186,10 +270,10 @@ powernv_smp_first_cpu(platform_t plat, struct cpuref *
return (ENOENT);
cpuref->cr_hwref = cpu;
- res = OF_getprop(cpu, "ibm,ppc-interrupt-server#s", &cpuid,
+ res = OF_getencprop(cpu, "ibm,ppc-interrupt-server#s", &cpuid,
sizeof(cpuid));
if (res <= 0)
- res = OF_getprop(cpu, "reg", &cpuid, sizeof(cpuid));
+ res = OF_getencprop(cpu, "reg", &cpuid, sizeof(cpuid));
if (res <= 0)
cpuid = 0;
cpuref->cr_cpuid = cpuid;
@@ -208,7 +292,7 @@ powernv_smp_next_cpu(platform_t plat, struct cpuref *c
res = OF_getproplen(cpuref->cr_hwref, "ibm,ppc-interrupt-server#s");
if (res > 0) {
cell_t interrupt_servers[res/sizeof(cell_t)];
- OF_getprop(cpuref->cr_hwref, "ibm,ppc-interrupt-server#s",
+ OF_getencprop(cpuref->cr_hwref, "ibm,ppc-interrupt-server#s",
interrupt_servers, res);
for (i = 0; i < res/sizeof(cell_t) - 1; i++) {
if (interrupt_servers[i] == cpuref->cr_cpuid) {
@@ -230,10 +314,10 @@ powernv_smp_next_cpu(platform_t plat, struct cpuref *c
return (ENOENT);
cpuref->cr_hwref = cpu;
- res = OF_getprop(cpu, "ibm,ppc-interrupt-server#s", &cpuid,
+ res = OF_getencprop(cpu, "ibm,ppc-interrupt-server#s", &cpuid,
sizeof(cpuid));
if (res <= 0)
- res = OF_getprop(cpu, "reg", &cpuid, sizeof(cpuid));
+ res = OF_getencprop(cpu, "reg", &cpuid, sizeof(cpuid));
if (res <= 0)
cpuid = 0;
cpuref->cr_cpuid = cpuid;
@@ -256,6 +340,10 @@ powernv_smp_get_bsp(platform_t plat, struct cpuref *cp
if (res < 0)
return (ENOENT);
+ /* XXX: FDT from kexec lies sometimes. PIR seems not to. */
+ if (cpuid == 0)
+ cpuid = powernv_boot_pir;
+
cpuref->cr_cpuid = cpuid;
if (powernv_smp_first_cpu(plat, &i) != 0)
@@ -299,7 +387,7 @@ powernv_smp_topo(platform_t plat)
ncores = ncpus = 0;
last_pc = NULL;
- for (i = 0; i <= mp_maxid; i++) {
+ CPU_FOREACH(i) {
pc = pcpu_find(i);
if (pc == NULL)
continue;
@@ -319,7 +407,11 @@ powernv_smp_topo(platform_t plat)
if (ncpus == ncores)
return (smp_topo_none());
+#ifdef NOTYET /* smp_topo_1level() fails with non-consecutive CPU IDs */
return (smp_topo_1level(CG_SHARE_L1, ncpus / ncores, CG_FLAG_SMT));
+#else
+ return (smp_topo_none());
+#endif
}
#endif
@@ -333,6 +425,9 @@ powernv_reset(platform_t platform)
static void
powernv_smp_ap_init(platform_t platform)
{
+
+ /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
+ mtspr(SPR_LPCR, LPCR_LPES);
}
static void
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