Author: wma
Date: Thu Jan 11 09:39:38 2018
New Revision: 327814
URL: https://svnweb.freebsd.org/changeset/base/327814
Log:
PowerNV: set LPCR[LPES] correctly
Make sure to set LPCR[LPES] so that external interrupts set SRR0 and SRR1
instead of HSRR0 and HSRR1. Without this, external interrupt handlers would
get the wrong MSR value when executing, causing eventual madness.
Created by: Nathan Whitehorn <nwhiteh...@freebsd.org>
Submitted by: Wojciech Macek <w...@freebsd.org>
Sponsored by: FreeBSD Foundation
Modified:
head/sys/powerpc/include/spr.h
head/sys/powerpc/powernv/platform_powernv.c
Modified: head/sys/powerpc/include/spr.h
==============================================================================
--- head/sys/powerpc/include/spr.h Thu Jan 11 09:34:33 2018
(r327813)
+++ head/sys/powerpc/include/spr.h Thu Jan 11 09:39:38 2018
(r327814)
@@ -199,6 +199,9 @@
#define FSL_E300C3 0x8085
#define FSL_E300C4 0x8086
+#define SPR_LPCR 0x13e /* Logical Partitioning Control
*/
+#define LPCR_LPES 0x008 /* Bit 60 */
+
#define SPR_EPCR 0x133
#define EPCR_EXTGS 0x80000000
#define EPCR_DTLBGS 0x40000000
Modified: head/sys/powerpc/powernv/platform_powernv.c
==============================================================================
--- head/sys/powerpc/powernv/platform_powernv.c Thu Jan 11 09:34:33 2018
(r327813)
+++ head/sys/powerpc/powernv/platform_powernv.c Thu Jan 11 09:39:38 2018
(r327814)
@@ -118,6 +118,9 @@ powernv_attach(platform_t plat)
cpu_idle_hook = powernv_cpu_idle;
+ /* Direct interrupts to SRR instead of HSRR */
+ mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_LPES);
+
return (0);
}
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