Author: nwhitehorn
Date: Fri Dec 29 20:25:15 2017
New Revision: 327357
URL: https://svnweb.freebsd.org/changeset/base/327357
Log:
Maintain alignment of in-code 64-bit quantities by design rather than luck.
If these are not aligned, the linker has to emit a different type of
relocation that the early boot self-relocation code cannot handle, even
in principle, resulting in them being set to zero and the kernel crashing.
MFC after: 1 week
Modified:
head/sys/powerpc/aim/trap_subr64.S
Modified: head/sys/powerpc/aim/trap_subr64.S
==============================================================================
--- head/sys/powerpc/aim/trap_subr64.S Fri Dec 29 20:00:19 2017
(r327356)
+++ head/sys/powerpc/aim/trap_subr64.S Fri Dec 29 20:25:15 2017
(r327357)
@@ -297,7 +297,8 @@ dtrace_invop_calltrap_addr:
* not still hanging around in the trap handling region
* once the MMU is turned on.
*/
- .globl CNAME(rstcode), CNAME(rstcodeend)
+ .globl CNAME(rstcode), CNAME(rstcodeend), CNAME(cpu_reset_handler)
+ .p2align 3
CNAME(rstcode):
/* Explicitly set MSR[SF] */
mfmsr %r9
@@ -305,8 +306,9 @@ CNAME(rstcode):
insrdi %r9,%r8,1,0
mtmsrd %r9
isync
+
bl 1f
- .llong cpu_reset
+ .llong cpu_reset_handler /* Make sure to maintain 8-byte alignment */
1: mflr %r9
ld %r9,0(%r9)
mtlr %r9
@@ -314,7 +316,7 @@ CNAME(rstcode):
blr
CNAME(rstcodeend):
-cpu_reset:
+cpu_reset_handler:
GET_TOCBASE(%r2)
ld %r1,TOC_REF(tmpstk)(%r2) /* get new SP */
@@ -569,6 +571,7 @@ CNAME(aliend):
* Has to handle standard pagetable spills
*/
.globl CNAME(dsitrap),CNAME(dsiend)
+ .p2align 3
CNAME(dsitrap):
mtsprg1 %r1 /* save SP */
GET_CPUINFO(%r1)
@@ -831,6 +834,7 @@ dbleave:
* In case of KDB we want a separate trap catcher for it
*/
.globl CNAME(dblow),CNAME(dbend)
+ .p2align 3
CNAME(dblow):
mtsprg1 %r1 /* save SP */
mtsprg2 %r29 /* save r29 */
@@ -859,6 +863,7 @@ CNAME(dblow):
std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
mflr %r28 /* save LR */
+ nop /* alignment */
bl 9f /* Begin branch */
.llong dbtrap
9: mflr %r1
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