Author: zbb Date: Tue Jun 20 11:09:38 2017 New Revision: 320141 URL: https://svnweb.freebsd.org/changeset/base/320141
Log: Implement workaround for Armada 38X family HW issue between CPU and devices There is a hardware problem between Cortex-A9 CPUs and on-chip devices in Armada 38X SoCs that may cause hang on heavy load. This can be however worked around by mapping all registers and PCI IO as strongly ordered instead of device memory. Submitted by: Zbigniew Bodek <z...@semihalf.com> Reviewed by: mmel Tested by: mw_semihalf.com Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D10218 Modified: head/sys/arm/mv/mv_machdep.c Modified: head/sys/arm/mv/mv_machdep.c ============================================================================== --- head/sys/arm/mv/mv_machdep.c Tue Jun 20 08:44:03 2017 (r320140) +++ head/sys/arm/mv/mv_machdep.c Tue Jun 20 11:09:38 2017 (r320141) @@ -59,6 +59,7 @@ __FBSDID("$FreeBSD$"); #include <machine/cpu-v4.h> #else #include <machine/cpu-v6.h> +#include <machine/pte-v6.h> #endif #include <arm/mv/mvreg.h> /* XXX */ @@ -257,6 +258,15 @@ platform_late_init(void) #endif #if defined(SOC_MV_ARMADA38X) + /* + * Workaround for Marvell Armada38X family HW issue + * between Cortex-A9 CPUs and on-chip devices that may + * cause hang on heavy load. + * To avoid that, map all registers including PCIe IO + * as strongly ordered instead of device memory. + */ + pmap_remap_vm_attr(PTE2_ATTR_DEVICE, PTE2_ATTR_SO); + /* Set IO Sync Barrier bit for all Mbus devices */ if (armada38x_win_set_iosync_barrier() != 0) printf("WARNING: could not map CPU Subsystem registers\n"); _______________________________________________ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
