Author: avg
Date: Sat Apr 8 14:16:42 2017
New Revision: 316643
URL: https://svnweb.freebsd.org/changeset/base/316643
Log:
use msr 0xc001100c to discover multi-node AMD processors
This is applicable only to the older processors that do not have the AMD
Topology extension.
Opteron 6100-series "Magny-Cours" processors had multiple nodes within a
package and didn't have the Topology extension. Without this change
FreeBSD would assume that those processors have a single L3 cache shared
by all cores while, in fact, each node has its own L3 cache.
Many thanks to Freddie Cash <fjwc...@gmail.com> for providing valuable
hardware information.
MFC after: 2 weeks
Modified:
head/sys/x86/x86/mp_x86.c
Modified: head/sys/x86/x86/mp_x86.c
==============================================================================
--- head/sys/x86/x86/mp_x86.c Sat Apr 8 10:00:39 2017 (r316642)
+++ head/sys/x86/x86/mp_x86.c Sat Apr 8 14:16:42 2017 (r316643)
@@ -236,7 +236,9 @@ static void
topo_probe_amd(void)
{
u_int p[4];
+ uint64_t v;
int level;
+ int nodes_per_socket;
int share_count;
int type;
int i;
@@ -295,13 +297,18 @@ topo_probe_amd(void)
caches[1].present = 1;
}
if (((p[3] >> 18) & 0x3fff) != 0) {
-
- /*
- * TODO: Account for dual-node processors
- * where each node within a package has its own
- * L3 cache.
- */
- caches[2].id_shift = pkg_id_shift;
+ nodes_per_socket = 1;
+ if ((amd_feature2 & AMDID2_NODE_ID) != 0) {
+ /*
+ * Handle multi-node processors that
+ * have multiple chips, each with its
+ * own L3 cache, on the same die.
+ */
+ v = rdmsr(0xc001100c);
+ nodes_per_socket = 1 + ((v >> 3) & 0x7);
+ }
+ caches[2].id_shift =
+ pkg_id_shift - mask_width(nodes_per_socket);
caches[2].present = 1;
}
}
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