Author: wma Date: Wed Jan 25 10:32:57 2017 New Revision: 312748 URL: https://svnweb.freebsd.org/changeset/base/312748
Log: Enable optional soft reset in AHCI It occurred that some Marvell integrated controllers require additional time after soft reset to work properly. Introduce new quirk (AHCI_Q_MRVL_SR_DEL), that enable such operation. Submitted by: Konrad Adamczyk <k...@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: mav Differential revision: https://reviews.freebsd.org/D9221 Modified: head/sys/dev/ahci/ahci.c head/sys/dev/ahci/ahci.h Modified: head/sys/dev/ahci/ahci.c ============================================================================== --- head/sys/dev/ahci/ahci.c Wed Jan 25 10:31:16 2017 (r312747) +++ head/sys/dev/ahci/ahci.c Wed Jan 25 10:32:57 2017 (r312748) @@ -1598,6 +1598,14 @@ ahci_execute_transaction(struct ahci_slo } /* + * Some Marvell controllers require additional time + * after soft reset to work properly. Setup delay + * to 50ms after soft reset. + */ + if (ch->quirks & AHCI_Q_MRVL_SR_DEL) + DELAY(50000); + + /* * Marvell HBAs with non-RAID firmware do not wait for * readiness after soft reset, so we have to wait here. * Marvell RAIDs do not have this problem, but instead Modified: head/sys/dev/ahci/ahci.h ============================================================================== --- head/sys/dev/ahci/ahci.h Wed Jan 25 10:31:16 2017 (r312747) +++ head/sys/dev/ahci/ahci.h Wed Jan 25 10:32:57 2017 (r312748) @@ -598,6 +598,7 @@ enum ahci_err_type { #define AHCI_Q_FORCE_PI 0x00040000 #define AHCI_Q_RESTORE_CAP 0x00080000 #define AHCI_Q_NOMSIX 0x00100000 +#define AHCI_Q_MRVL_SR_DEL 0x00200000 #define AHCI_Q_BIT_STRING \ "\020" \ _______________________________________________ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
