Author: np
Date: Thu Dec 15 02:05:29 2016
New Revision: 310100
URL: https://svnweb.freebsd.org/changeset/base/310100
Log:
cxgbe(4): Deal with compressed error vectors.
MFC after: 3 days
Sponsored by: Chelsio Communications
Modified:
head/sys/dev/cxgbe/common/common.h
head/sys/dev/cxgbe/common/t4_hw.c
head/sys/dev/cxgbe/common/t4_msg.h
head/sys/dev/cxgbe/t4_sge.c
Modified: head/sys/dev/cxgbe/common/common.h
==============================================================================
--- head/sys/dev/cxgbe/common/common.h Thu Dec 15 01:45:31 2016
(r310099)
+++ head/sys/dev/cxgbe/common/common.h Thu Dec 15 02:05:29 2016
(r310100)
@@ -227,7 +227,7 @@ struct tp_params {
uint32_t vlan_pri_map;
uint32_t ingress_config;
- uint32_t rx_pkt_encap;
+ __be16 err_vec_mask;
int8_t fcoe_shift;
int8_t port_shift;
Modified: head/sys/dev/cxgbe/common/t4_hw.c
==============================================================================
--- head/sys/dev/cxgbe/common/t4_hw.c Thu Dec 15 01:45:31 2016
(r310099)
+++ head/sys/dev/cxgbe/common/t4_hw.c Thu Dec 15 02:05:29 2016
(r310100)
@@ -8020,12 +8020,17 @@ int t4_init_tp_params(struct adapter *ad
read_filter_mode_and_ingress_config(adap);
/*
- * For T6, cache the adapter's compressed error vector
- * and passing outer header info for encapsulated packets.
+ * Cache a mask of the bits that represent the error vector portion of
+ * rx_pkt.err_vec. T6+ can use a compressed error vector to make room
+ * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
*/
+ tpp->err_vec_mask = htobe16(0xffff);
if (chip_id(adap) > CHELSIO_T5) {
v = t4_read_reg(adap, A_TP_OUT_CONFIG);
- tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
+ if (v & F_CRXPKTENC) {
+ tpp->err_vec_mask =
+ htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
+ }
}
return 0;
Modified: head/sys/dev/cxgbe/common/t4_msg.h
==============================================================================
--- head/sys/dev/cxgbe/common/t4_msg.h Thu Dec 15 01:45:31 2016
(r310099)
+++ head/sys/dev/cxgbe/common/t4_msg.h Thu Dec 15 02:05:29 2016
(r310100)
@@ -2014,7 +2014,7 @@ struct cpl_rx_pkt {
#define S_T6_COMPR_RXERR_VEC 0
#define M_T6_COMPR_RXERR_VEC 0x3F
-#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_LEN)
+#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
#define G_T6_COMPR_RXERR_VEC(x) \
(((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
Modified: head/sys/dev/cxgbe/t4_sge.c
==============================================================================
--- head/sys/dev/cxgbe/t4_sge.c Thu Dec 15 01:45:31 2016 (r310099)
+++ head/sys/dev/cxgbe/t4_sge.c Thu Dec 15 02:05:29 2016 (r310100)
@@ -1808,7 +1808,7 @@ t4_eth_rx(struct sge_iq *iq, const struc
M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
m0->m_pkthdr.flowid = be32toh(rss->hash_val);
- if (cpl->csum_calc && !cpl->err_vec) {
+ if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
if (ifp->if_capenable & IFCAP_RXCSUM &&
cpl->l2info & htobe32(F_RXF_IP)) {
m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
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