Author: br
Date: Thu Nov 17 11:31:13 2016
New Revision: 308746
URL: https://svnweb.freebsd.org/changeset/base/308746
Log:
Import Ingenic CI20 (jz4780) DTS files.
Submitted by: kan
Sponsored by: DARPA, AFRL
Added:
head/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h (contents, props
changed)
head/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h (contents,
props changed)
head/sys/gnu/dts/mips/ingenic/
head/sys/gnu/dts/mips/ingenic/ci20.dts (contents, props changed)
head/sys/gnu/dts/mips/ingenic/jz4780.dtsi (contents, props changed)
Added: head/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h Thu Nov 17
11:31:13 2016 (r308746)
@@ -0,0 +1,49 @@
+#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
+#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
+
+/*
+ * Request type numbers for the JZ4780 DMA controller (written to the DRTn
+ * register for the channel).
+ */
+#define JZ4780_DMA_I2S1_TX 0x4
+#define JZ4780_DMA_I2S1_RX 0x5
+#define JZ4780_DMA_I2S0_TX 0x6
+#define JZ4780_DMA_I2S0_RX 0x7
+#define JZ4780_DMA_AUTO 0x8
+#define JZ4780_DMA_SADC_RX 0x9
+#define JZ4780_DMA_UART4_TX 0xc
+#define JZ4780_DMA_UART4_RX 0xd
+#define JZ4780_DMA_UART3_TX 0xe
+#define JZ4780_DMA_UART3_RX 0xf
+#define JZ4780_DMA_UART2_TX 0x10
+#define JZ4780_DMA_UART2_RX 0x11
+#define JZ4780_DMA_UART1_TX 0x12
+#define JZ4780_DMA_UART1_RX 0x13
+#define JZ4780_DMA_UART0_TX 0x14
+#define JZ4780_DMA_UART0_RX 0x15
+#define JZ4780_DMA_SSI0_TX 0x16
+#define JZ4780_DMA_SSI0_RX 0x17
+#define JZ4780_DMA_SSI1_TX 0x18
+#define JZ4780_DMA_SSI1_RX 0x19
+#define JZ4780_DMA_MSC0_TX 0x1a
+#define JZ4780_DMA_MSC0_RX 0x1b
+#define JZ4780_DMA_MSC1_TX 0x1c
+#define JZ4780_DMA_MSC1_RX 0x1d
+#define JZ4780_DMA_MSC2_TX 0x1e
+#define JZ4780_DMA_MSC2_RX 0x1f
+#define JZ4780_DMA_PCM0_TX 0x20
+#define JZ4780_DMA_PCM0_RX 0x21
+#define JZ4780_DMA_SMB0_TX 0x24
+#define JZ4780_DMA_SMB0_RX 0x25
+#define JZ4780_DMA_SMB1_TX 0x26
+#define JZ4780_DMA_SMB1_RX 0x27
+#define JZ4780_DMA_SMB2_TX 0x28
+#define JZ4780_DMA_SMB2_RX 0x29
+#define JZ4780_DMA_SMB3_TX 0x2a
+#define JZ4780_DMA_SMB3_RX 0x2b
+#define JZ4780_DMA_SMB4_TX 0x2c
+#define JZ4780_DMA_SMB4_RX 0x2d
+#define JZ4780_DMA_DES_TX 0x2e
+#define JZ4780_DMA_DES_RX 0x2f
+
+#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
Added: head/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/gnu/dts/include/dt-bindings/net/rfkill-regulator.h Thu Nov 17
11:31:13 2016 (r308746)
@@ -0,0 +1,23 @@
+/*
+ * This header provides macros for rfkill-regulator bindings.
+ *
+ * Copyright (C) 2014 Marek Belisko <ma...@goldelico.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_RFKILL_REGULATOR_H__
+#define __DT_BINDINGS_RFKILL_REGULATOR_H__
+
+
+#define RFKILL_TYPE_ALL (0)
+#define RFKILL_TYPE_WLAN (1)
+#define RFKILL_TYPE_BLUETOOTH (2)
+#define RFKILL_TYPE_UWB (3)
+#define RFKILL_TYPE_WIMAX (4)
+#define RFKILL_TYPE_WWAN (5)
+#define RFKILL_TYPE_GPS (6)
+#define RFKILL_TYPE_FM (7)
+#define RFKILL_TYPE_NFC (8)
+
+#endif /* __DT_BINDINGS_RFKILL_REGULATOR_H__ */
Added: head/sys/gnu/dts/mips/ingenic/ci20.dts
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/gnu/dts/mips/ingenic/ci20.dts Thu Nov 17 11:31:13 2016
(r308746)
@@ -0,0 +1,395 @@
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/rfkill-regulator.h>
+#include "jz4780.dtsi"
+
+/ {
+ compatible = "imgtec,ci20", "ingenic,jz4780";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000
+ 0x30000000 0x30000000>;
+ };
+
+ audio: audio-ci20 {
+ compatible = "ingenic,ci20-audio";
+ ingenic,i2s-controller = <&i2s>;
+ ingenic,codec = <&codec>;
+ };
+
+ eth0_power: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "eth0_power";
+ gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
+
+ hdmi_power: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_power";
+ gpio = <&gpa 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ wifi_power: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi_power_gpio";
+ gpio = <&gpb 19 0>;
+ enable-active-high;
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ };
+
+ /* HACK: Keeping wifi reset high. No simple driver fix */
+ wifi_reset: fixedregulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi_reset_gpio";
+ gpio = <&gpf 7 0>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* HACK: Keeping BT reset high. No simple driver fix */
+ bt_reset: fixedregulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "bt_reset_gpio";
+ gpio = <&gpf 8 0>;
+ enable-active-high;
+ };
+
+ /* HACK: Keeping BT_reg_on high. No simple driver fix */
+ bt_reg_on: fixedregulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "bt_reg_on_gpio";
+ gpio = <&gpf 4 0>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* HACK: Keeping BT wake high. No simple driver fix */
+ bt_wake: fixedregulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "bt_wake_gpio";
+ gpio = <&gpf 5 0>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
+ };
+
+ bt-rfkill {
+ compatible = "rfkill-regulator";
+ label = "bt-reset";
+ type = <RFKILL_TYPE_BLUETOOTH>;
+ vrfkill-supply = <&bt_reset>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led3 {
+ gpios = <&gpc 0 0>;
+ linux,default-trigger = "cpu0";
+ };
+ led2 {
+ gpios = <&gpc 1 0>;
+ linux,default-trigger = "cpu1";
+ };
+ led1 {
+ gpios = <&gpc 2 0>;
+ linux,default-trigger = "nand-disk";
+ };
+ led0 {
+ gpios = <&gpc 3 0>;
+ linux,default-trigger = "none";
+ };
+ };
+};
+
+&ext {
+ clock-frequency = <48000000>;
+};
+
+&msc0 {
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_msc0_pe>;
+};
+
+&msc1 {
+ bus-width = <4>;
+ max-frequency = <24000000>;
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_msc1_pd>;
+ vmmc-supply = <&wifi_power>;
+};
+
+&ehci {
+ ingenic,vbus-gpio = <&gpf 15 0>;
+};
+
+&ohci {
+ ingenic,vbus-gpio = <&gpf 15 0>;
+};
+
+&nemc {
+ /*
+ * Only CLE/ALE are needed for the devices that are connected, rather
+ * than the full address line set.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_data
+ &pins_nemc_cle_ale
+ &pins_nemc_rd_we
+ &pins_nemc_frd_fwe>;
+
+ nand: nand@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x1000000>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ ingenic,bch-device = <&bch>;
+ ingenic,ecc-size = <1024>;
+ ingenic,ecc-strength = <24>;
+
+ ingenic,busy-gpio = <&gpa 20 GPIO_ACTIVE_LOW>;
+ ingenic,wp-gpio = <&gpf 22 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x800000>;
+ };
+
+ partition@0x800000 {
+ label = "u-boot";
+ reg = <0x0 0x800000 0x0 0x200000>;
+ };
+
+ partition@0xa00000 {
+ label = "u-boot-env";
+ reg = <0x0 0xa00000 0x0 0x200000>;
+ };
+
+ partition@0xc00000 {
+ label = "boot";
+ reg = <0x0 0xc00000 0x0 0x4000000>;
+ };
+
+ partition@0x8c00000 {
+ label = "system";
+ reg = <0x0 0x4c00000 0x1 0xfb400000>;
+ };
+ };
+
+ dm9000@6 {
+ compatible = "davicom,dm9000";
+ davicom,no-eeprom;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs6>;
+
+ reg = <6 0x0 1 /* addr */
+ 6 0x2 1>; /* data */
+
+ ingenic,nemc-tAS = <15>;
+ ingenic,nemc-tAH = <10>;
+ ingenic,nemc-tBP = <20>;
+ ingenic,nemc-tAW = <50>;
+ ingenic,nemc-tSTRV = <100>;
+
+ reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <ð0_power>;
+
+ interrupt-parent = <&gpe>;
+ interrupts = <19 0x4>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart0_data>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart1_data>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2_dataplusflow>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart3_data>;
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart4_data>;
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c0_data>;
+
+ pmic: act8600@5a {
+ compatible = "active-semi,act8600";
+ reg = <0x5a>;
+
+ regulators {
+ vcore1v_reg: DCDC_REG1 {
+ regulator-name = "vcore1v2";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ };
+
+ vddmem1v5_reg: DCDC_REG2 {
+ regulator-name = "vddmem1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vccio3v3_reg: DCDC_REG3 {
+ regulator-name = "vccio3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vcc2v5_reg: LDO_REG5 {
+ regulator-name = "vcc2.5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vwifi_reg: LDO_REG6 {
+ regulator-name = "vwifi3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcim2v8_reg: LDO_REG7 {
+ regulator-name = "vcim2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vcim1v5_reg: LDO_REG8 {
+ regulator-name = "vcim1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ /* Do not disable RTC as they connect to reset line */
+ vrtc1v8_reg: LDO_REG9 {
+ regulator-name = "vrtc1v8";
+ regulator-always-on;
+ };
+
+ vrtc1v1_reg: LDO_REG10 {
+ regulator-name = "vrtc1v2";
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c1_data>;
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c2_data>;
+
+ ov5640@0x3C {
+ compatible = "omnivision,ov5640";
+ reg = <0x3C>;
+
+ core-supply = <&vcim1v5_reg>;
+ analog-supply = <&vcim2v8_reg>;
+
+ gpio-enable = <&gpb 18 0>;
+ gpio-reset = <&gpb 26 0>;
+
+ remote = <&cim>;
+ port {
+ ov5640_1: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&cim>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c3_data>;
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_i2c4_data_pf>;
+};
+
+&cim {
+ clock-frequency = <24000000>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Parallel bus endpoint */
+ camera: endpoint@0 {
+ reg = <0>; /* Local endpoint # */
+ remote-endpoint = <&ov5640_1>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <1>; /* Active high */
+ pclk-sample = <0>; /* Falling */
+ };
+ };
+};
Added: head/sys/gnu/dts/mips/ingenic/jz4780.dtsi
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/gnu/dts/mips/ingenic/jz4780.dtsi Thu Nov 17 11:31:13 2016
(r308746)
@@ -0,0 +1,768 @@
+#include <dt-bindings/clock/jz4780-cgu.h>
+#include <dt-bindings/dma/jz4780-dma.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,jz4780";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ };
+ cpu1: cpu@1 {
+ compatible = "ingenic,xburst";
+ reg = <1>;
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ };
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: intc@10001000 {
+ compatible = "ingenic,jz4780-intc";
+ reg = <0x10001000 0x50>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ ext: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ rtc: rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ cgu: jz4780-cgu@10000000 {
+ compatible = "ingenic,jz4780-cgu";
+ reg = <0x10000000 0x100>;
+
+ clocks = <&ext>, <&rtc>;
+ clock-names = "ext", "rtc";
+
+ #clock-cells = <1>;
+ };
+
+ gpu: jz4780-sgx@13040000 {
+ compatible = "ingenic,jz4780-sgx";
+ reg = <0x13040000 0x4000>;
+
+ clocks = <&cgu JZ4780_CLK_GPU>;
+ clock-names = "gpu";
+
+ interrupt-parent = <&intc>;
+ interrupts = <63>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <>;
+
+ tcu@0x10002000 {
+ compatible = "ingenic,jz4780-tcu";
+ reg = <0x10002000 0x140>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+ };
+
+ watchdog: jz47xx-watchdog@0x10002000 {
+ compatible = "ingenic,jz4780-watchdog";
+ reg = <0x10002000 0x100>;
+
+ clocks = <&rtc>;
+ clock-names = "rtc";
+ };
+
+ rtcdev: rtcdev@10003000 {
+ compatible = "ingenic,jz4780-rtc";
+ reg = <0x10003000 0x4c>;
+ interrupt-parent = <&intc>;
+ interrupts = <32>;
+ };
+
+ i2s: i2s@10020000 {
+ compatible = "ingenic,jz4780-i2s";
+ reg = <0x10020000 0x94>;
+
+ clocks = <&cgu JZ4780_CLK_AIC>, <&cgu
JZ4780_CLK_I2SPLL>;
+ clock-names = "aic", "i2s";
+
+ dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma
JZ4780_DMA_I2S0_TX 0 0xffffffff>;
+ dma-names = "rx" , "tx";
+
+ };
+
+ codec: codec@100200a4 {
+ compatible = "ingenic,jz4780-codec";
+ reg = <0x100200a4 0x8>;
+
+ clocks = <&cgu JZ4780_CLK_I2SPLL>;
+ clock-names = "i2s";
+
+ };
+
+ pinctrl@0x10010000 {
+ compatible = "ingenic,jz4780-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ gpa: gpa {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+
+ ingenic,pull-ups = <0x3fffffff>;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+
+ ingenic,pull-downs = <0x000f0c03>;
+ ingenic,pull-ups = <0xfff0030c>;
+ };
+
+ gpc: gpc {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+
+ ingenic,pull-ups = <0xffffffff>;
+ };
+
+ gpd: gpd {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+
+ ingenic,pull-downs = <0x0000b000>;
+ ingenic,pull-ups = <0xffff4fff>;
+ };
+
+ gpe: gpe {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <13>;
+
+ ingenic,pull-downs = <0x00000483>;
+ ingenic,pull-ups = <0xfffffb7c>;
+ };
+
+ gpf: gpf {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <12>;
+
+ ingenic,pull-downs = <0x00580ff0>;
+ ingenic,pull-ups = <0xffa7f00f>;
+ };
+
+ pincfg_nobias: nobias {
+ bias-disable;
+ };
+
+ pincfg_pull_up: pull_up {
+ bias-pull-up;
+ };
+
+ pincfg_pull_down: pull_down {
+ bias-pull-down;
+ };
+
+ pinfunc_uart0: uart0 {
+ pins_uart0_data: uart0-data {
+ ingenic,pins = <&gpf 0 0
&pincfg_pull_up /* rxd */
+ &gpf 3 0
&pincfg_nobias>; /* txd */
+ };
+
+ pins_uart0_dataplusflow: uart0-dataplusflow {
+ ingenic,pins = <&gpf 0 0
&pincfg_pull_up /* rxd */
+ &gpf 1 0
&pincfg_nobias /* cts */
+ &gpf 2 0
&pincfg_nobias /* rts */
+ &gpf 3 0
&pincfg_nobias>; /* txd */
+ };
+ };
+
+ pinfunc_uart1: uart1 {
+ pins_uart1_data: uart1-data {
+ ingenic,pins = <&gpd 26 0
&pincfg_pull_up /* rxd */
+ &gpd 28 0
&pincfg_nobias>; /* txd */
+ };
+
+ pins_uart1_dataplusflow: uart1-dataplusflow {
+ ingenic,pins = <&gpd 26 0
&pincfg_pull_up /* rxd */
+ &gpd 27 0
&pincfg_nobias /* cts */
+ &gpd 29 0
&pincfg_nobias /* rts */
+ &gpd 28 0
&pincfg_nobias>; /* txd */
+ };
+ };
+
+ pinfunc_uart2: uart2 {
+ pins_uart2_data: uart2-data {
+ ingenic,pins = <&gpd 6 1
&pincfg_nobias /* rxd */
+ &gpd 7 1
&pincfg_nobias>; /* txd */
+ };
+
+ pins_uart2_dataplusflow: uart2-dataplusflow {
+ ingenic,pins = <&gpd 6 1
&pincfg_nobias /* rxd */
+ &gpd 5 1
&pincfg_nobias /* cts */
+ &gpd 4 1
&pincfg_nobias /* rts */
+ &gpd 7 1
&pincfg_nobias>; /* txd */
+ };
+ };
+
+ pinfunc_uart3: uart3 {
+ pins_uart3_data: uart3-data {
+ ingenic,pins = <&gpd 12 0
&pincfg_pull_down /* rxd */
+ &gpe 5 1
&pincfg_nobias>; /* txd */
+ };
+
+ pins_uart3_dataplusflow: uart3-dataplusflow {
+ ingenic,pins = <&gpd 12 0
&pincfg_pull_down /* rxd */
+ &gpe 5 1
&pincfg_nobias /* txd */
+ &gpe 8 0
&pincfg_nobias /* cts */
+ &gpe 9 0
&pincfg_nobias>; /* rts */
+ };
+ };
+
+ pinfunc_uart4: uart4 {
+ pins_uart4_data: uart4-data {
+ ingenic,pins = <&gpc 20 2
&pincfg_pull_up /* rxd */
+ &gpc 10 2
&pincfg_nobias>; /* txd */
+ };
+ };
+
+ pinfunc_msc0: msc0 {
+ pins_msc0_pa: msc0-pa {
+ ingenic,pins = <&gpa 4 1
&pincfg_nobias /* d4 */
+ &gpa 5 1
&pincfg_nobias /* d5 */
+ &gpa 6 1
&pincfg_nobias /* d6 */
+ &gpa 7 1
&pincfg_nobias /* d7 */
+ &gpa 18 1
&pincfg_nobias /* clk */
+ &gpa 19 1
&pincfg_nobias /* cmd */
+ &gpa 20 1
&pincfg_nobias /* d0 */
+ &gpa 21 1
&pincfg_nobias /* d1 */
+ &gpa 22 1
&pincfg_nobias /* d2 */
+ &gpa 23 1
&pincfg_nobias /* d3 */
+ &gpa 24 1
&pincfg_nobias>; /* rst */
+ };
+
+ pins_msc0_pe: msc0-pe {
+ ingenic,pins = <&gpe 20 0
&pincfg_nobias /* d0 */
+ &gpe 21 0
&pincfg_nobias /* d1 */
+ &gpe 22 0
&pincfg_nobias /* d2 */
+ &gpe 23 0
&pincfg_nobias /* d3 */
+ &gpe 28 0
&pincfg_nobias /* clk */
+ &gpe 29 0
&pincfg_nobias>; /* cmd */
+ };
+ };
+
+ pinfunc_msc1: msc1 {
+ pins_msc1_pd: msc1-pd {
+ ingenic,pins = <&gpd 20 0
&pincfg_nobias /* d0 */
+ &gpd 21 0
&pincfg_nobias /* d1 */
+ &gpd 22 0
&pincfg_nobias /* d2 */
+ &gpd 23 0
&pincfg_nobias /* d3 */
+ &gpd 24 0
&pincfg_nobias /* clk */
+ &gpd 25 0
&pincfg_nobias>; /* cmd */
+ };
+
+ pins_msc1_pe: msc1-pe {
+ ingenic,pins = <&gpe 20 1
&pincfg_nobias /* d0 */
+ &gpe 21 1
&pincfg_nobias /* d1 */
+ &gpe 22 1
&pincfg_nobias /* d2 */
+ &gpe 23 1
&pincfg_nobias /* d3 */
+ &gpe 28 1
&pincfg_nobias /* clk */
+ &gpe 29 1
&pincfg_nobias>; /* cmd */
+ };
+ };
+
+ pinfunc_nemc: nemc {
+ pins_nemc_data: nemc-data {
+ ingenic,pins = <&gpa 0 0 &pincfg_nobias
/* sd0 */
+ &gpa 1 0 &pincfg_nobias
/* sd1 */
+ &gpa 2 0 &pincfg_nobias
/* sd2 */
+ &gpa 3 0 &pincfg_nobias
/* sd3 */
+ &gpa 4 0 &pincfg_nobias
/* sd4 */
+ &gpa 5 0 &pincfg_nobias
/* sd5 */
+ &gpa 6 0 &pincfg_nobias
/* sd6 */
+ &gpa 7 0
&pincfg_nobias>; /* sd7 */
+ };
+
+ pins_nemc_cle_ale: nemc-cle-ale {
+ ingenic,pins = <&gpb 0 0 &pincfg_nobias
/* sa0_cl */
+ &gpb 1 0
&pincfg_nobias>; /* sa1_al */
+ };
+
+ pins_nemc_addr: nemc-addr {
+ ingenic,pins = <&gpb 0 0 &pincfg_nobias
/* sa0_cl */
+ &gpb 1 0 &pincfg_nobias
/* sa1_al */
+ &gpb 2 0 &pincfg_nobias
/* sa2 */
+ &gpb 3 0 &pincfg_nobias
/* sa3 */
+ &gpb 4 0 &pincfg_nobias
/* sa4 */
+ &gpb 5 0
&pincfg_nobias>; /* sa5 */
+ };
+
+ pins_nemc_rd_we: nemc-rd-we {
+ ingenic,pins = <&gpa 16 0
&pincfg_nobias /* rd */
+ &gpa 17 0
&pincfg_nobias>; /* we */
+ };
+
+ pins_nemc_frd_fwe: nemc-frd-fwe {
+ ingenic,pins = <&gpa 18 0
&pincfg_nobias /* rd */
+ &gpa 19 0
&pincfg_nobias>; /* we */
+ };
+
+ pins_nemc_cs1: nemc-cs1 {
+ ingenic,pins = <&gpa 21 0
&pincfg_nobias>; /* cs1 */
+ };
+
+ pins_nemc_cs6: nemc-cs6 {
+ ingenic,pins = <&gpa 26 0
&pincfg_nobias>; /* cs6 */
+ };
+ };
+
+ pinfunc_i2c0: i2c0 {
+ pins_i2c0_data: i2c0-data{
+ ingenic,pins = <&gpd 30 0
&pincfg_nobias /* sda */
+ &gpd 31 0
&pincfg_nobias>; /* sck */
+ };
+ };
+
+ pinfunc_i2c1: i2c1 {
+ pins_i2c1_data: i2c1-data{
+ ingenic,pins = <&gpe 30 0
&pincfg_nobias /* sda */
+ &gpe 31 0
&pincfg_nobias>; /* sck */
+ };
+ };
+
+ pinfunc_i2c2: i2c2 {
+ pins_i2c2_data: i2c2-data{
+ ingenic,pins = <&gpf 16 2
&pincfg_nobias /* sda */
+ &gpf 17 2
&pincfg_nobias>; /* sck */
+ };
+ };
+
+ pinfunc_i2c3: i2c3 {
+ pins_i2c3_data: i2c3-data{
+ ingenic,pins = <&gpd 10 1
&pincfg_nobias /* sda */
+ &gpd 11 1
&pincfg_nobias>; /* sck */
+ };
+ };
+
+ pinfunc_i2c4: i2c4 {
+ pins_i2c4_data: i2c4-data-pe{
+ ingenic,pins = <&gpe 12 1
&pincfg_nobias /* sda */
+ &gpe 13 1
&pincfg_nobias>; /* sck */
+ };
+
+ pins_i2c4_data_pf: i2c4-data-pf{
+ ingenic,pins = <&gpf 25 1
&pincfg_nobias /* hdmi_sda */
+ &gpf 24 1
&pincfg_nobias>; /* hdmi_sck */
+ };
+ };
+
+ pinfunc_cim: cim {
+ pins_cim: cim-pb {
+ ingenic,pins = <&gpb 6 0
&pincfg_nobias
+ &gpb 7 0
&pincfg_nobias
+ &gpb 8 0
&pincfg_nobias
+ &gpb 9 0
&pincfg_nobias
+ &gpb 10 0
&pincfg_nobias
+ &gpb 11 0
&pincfg_nobias
+ &gpb 12 0
&pincfg_nobias
+ &gpb 13 0
&pincfg_nobias
+ &gpb 14 0
&pincfg_nobias
+ &gpb 15 0
&pincfg_nobias
+ &gpb 16 0
&pincfg_nobias
+ &gpb 17 0
&pincfg_nobias>;
+ };
+ };
+ };
+
+ spi_gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-chipselects = <2>;
+
+ gpio-miso = <&gpe 14 0>;
+ gpio-sck = <&gpe 15 0>;
+ gpio-mosi = <&gpe 17 0>;
+ cs-gpios = <&gpe 16 0
+ &gpe 18 0>;
+
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ uart0: serial@10030000 {
+ compatible = "ingenic,jz4780-uart";
+ reg = <0x10030000 0x100>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <51>;
+
+ clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
+ clock-names = "baud", "module";
+ };
+
+ uart1: serial@10031000 {
+ compatible = "ingenic,jz4780-uart";
+ reg = <0x10031000 0x100>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <50>;
+
+ clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
+ clock-names = "baud", "module";
+ };
+
+ uart2: serial@10032000 {
+ compatible = "ingenic,jz4780-uart";
+ reg = <0x10032000 0x100>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <49>;
+
+ clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
+ clock-names = "baud", "module";
+ };
+
+ uart3: serial@10033000 {
+ compatible = "ingenic,jz4780-uart";
+ reg = <0x10033000 0x100>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <48>;
+
+ clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
+ clock-names = "baud", "module";
+ };
+
+ uart4: serial@10034000 {
+ compatible = "ingenic,jz4780-uart";
+ reg = <0x10034000 0x100>;
+ reg-shift = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <34>;
+
+ clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
+ clock-names = "baud", "module";
+ };
+
+ i2c0: i2c0@0x10050000 {
+ compatible = "ingenic,jz4780-i2c";
+ reg = <0x10050000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <60>;
+
+ clocks = <&cgu JZ4780_CLK_SMB0>;
+
+ #address-cells = <1>;
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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