Author: loos
Date: Thu Mar 17 06:23:48 2016
New Revision: 296980
URL: https://svnweb.freebsd.org/changeset/base/296980
Log:
Fixes a few style(9) issues, remove extra blank lines.
No functional changes.
Sponsored by: Rubicon Comunications (Netgate)
Modified:
head/sys/arm/ti/cpsw/if_cpsw.c
head/sys/arm/ti/cpsw/if_cpswreg.h
head/sys/arm/ti/cpsw/if_cpswvar.h
Modified: head/sys/arm/ti/cpsw/if_cpsw.c
==============================================================================
--- head/sys/arm/ti/cpsw/if_cpsw.c Thu Mar 17 04:21:57 2016
(r296979)
+++ head/sys/arm/ti/cpsw/if_cpsw.c Thu Mar 17 06:23:48 2016
(r296980)
@@ -148,8 +148,7 @@ static int cpsw_stats_sysctl(SYSCTL_HAND
* Packets with more segments than this will be defragmented before
* they are queued.
*/
-#define CPSW_TXFRAGS 8
-
+#define CPSW_TXFRAGS 8
/*
* TODO: The CPSW subsystem (CPSW_SS) can drive two independent PHYs
@@ -251,7 +250,7 @@ static struct cpsw_stat {
* Basic debug support.
*/
-#define IF_DEBUG(sc) if (sc->cpsw_if_flags & IFF_DEBUG)
+#define IF_DEBUG(sc) if (sc->cpsw_if_flags & IFF_DEBUG)
static void
cpsw_debugf_head(const char *funcname)
@@ -274,35 +273,34 @@ cpsw_debugf(const char *fmt, ...)
}
-#define CPSW_DEBUGF(a) do { \
- IF_DEBUG(sc) { \
- cpsw_debugf_head(__func__); \
- cpsw_debugf a; \
- } \
+#define CPSW_DEBUGF(a) do {
\
+ IF_DEBUG(sc) { \
+ cpsw_debugf_head(__func__); \
+ cpsw_debugf a; \
+ } \
} while (0)
-
/*
* Locking macros
*/
-#define CPSW_TX_LOCK(sc) do { \
+#define CPSW_TX_LOCK(sc) do {
\
mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
mtx_lock(&(sc)->tx.lock); \
} while (0)
-#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
-#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
+#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
+#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
-#define CPSW_RX_LOCK(sc) do { \
+#define CPSW_RX_LOCK(sc) do {
\
mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
mtx_lock(&(sc)->rx.lock); \
} while (0)
-#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock)
-#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED)
+#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock)
+#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED)
-#define CPSW_GLOBAL_LOCK(sc) do { \
- if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) != \
+#define CPSW_GLOBAL_LOCK(sc) do {
\
+ if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) != \
(mtx_owned(&(sc)->rx.lock) ? 1 : 0)) { \
panic("cpsw deadlock possibility detection!"); \
} \
@@ -310,12 +308,12 @@ cpsw_debugf(const char *fmt, ...)
mtx_lock(&(sc)->rx.lock); \
} while (0)
-#define CPSW_GLOBAL_UNLOCK(sc) do { \
- CPSW_RX_UNLOCK(sc); \
- CPSW_TX_UNLOCK(sc); \
+#define CPSW_GLOBAL_UNLOCK(sc) do {
\
+ CPSW_RX_UNLOCK(sc); \
+ CPSW_TX_UNLOCK(sc); \
} while (0)
-#define CPSW_GLOBAL_LOCK_ASSERT(sc) do { \
+#define CPSW_GLOBAL_LOCK_ASSERT(sc) do {
\
CPSW_TX_LOCK_ASSERT(sc); \
CPSW_RX_LOCK_ASSERT(sc); \
} while (0)
@@ -328,7 +326,7 @@ cpsw_debugf(const char *fmt, ...)
#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16))
-#define cpsw_cpdma_bd_paddr(sc, slot) \
+#define cpsw_cpdma_bd_paddr(sc, slot)
\
BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset)
#define cpsw_cpdma_read_bd(sc, slot, val)
\
bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
@@ -336,16 +334,16 @@ cpsw_debugf(const char *fmt, ...)
bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
#define cpsw_cpdma_write_bd_next(sc, slot, next_slot)
\
cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
-#define cpsw_cpdma_read_bd_flags(sc, slot) \
+#define cpsw_cpdma_read_bd_flags(sc, slot)
\
bus_read_2(sc->mem_res, slot->bd_offset + 14)
#define cpsw_write_hdp_slot(sc, queue, slot)
\
cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
-#define cpsw_read_cp(sc, queue) \
+#define cpsw_read_cp(sc, queue)
\
cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
-#define cpsw_write_cp(sc, queue, val) \
+#define cpsw_write_cp(sc, queue, val)
\
cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
-#define cpsw_write_cp_slot(sc, queue, slot) \
+#define cpsw_write_cp_slot(sc, queue, slot)
\
cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
#if 0
@@ -403,13 +401,12 @@ cpsw_dump_slot(struct cpsw_softc *sc, st
}
}
-#define CPSW_DUMP_SLOT(cs, slot) do { \
+#define CPSW_DUMP_SLOT(cs, slot) do { \
IF_DEBUG(sc) { \
cpsw_dump_slot(sc, slot); \
} \
} while (0)
-
static void
cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
{
@@ -429,13 +426,12 @@ cpsw_dump_queue(struct cpsw_softc *sc, s
printf("\n");
}
-#define CPSW_DUMP_QUEUE(sc, q) do { \
+#define CPSW_DUMP_QUEUE(sc, q) do { \
IF_DEBUG(sc) { \
cpsw_dump_queue(sc, q); \
} \
} while (0)
-
/*
*
* Device Probe, Attach, Detach.
@@ -456,7 +452,6 @@ cpsw_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
-
static void
cpsw_init_slots(struct cpsw_softc *sc)
{
@@ -1303,7 +1298,6 @@ cpsw_miibus_statchg(device_t dev)
*
*/
-
static void
cpsw_intr_rx(void *arg)
{
@@ -2266,4 +2260,3 @@ cpsw_add_sysctls(struct cpsw_softc *sc)
CTLFLAG_RD, NULL, "Watchdog Statistics");
cpsw_add_watchdog_sysctls(ctx, node, sc);
}
-
Modified: head/sys/arm/ti/cpsw/if_cpswreg.h
==============================================================================
--- head/sys/arm/ti/cpsw/if_cpswreg.h Thu Mar 17 04:21:57 2016
(r296979)
+++ head/sys/arm/ti/cpsw/if_cpswreg.h Thu Mar 17 06:23:48 2016
(r296980)
@@ -29,103 +29,103 @@
#ifndef _IF_CPSWREG_H
#define _IF_CPSWREG_H
-#define CPSW_SS_OFFSET 0x0000
-#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
-#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
-#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
-#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_OFFSET 0x0000
+#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
+#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
+#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
+#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
-#define CPSW_PORT_OFFSET 0x0100
+#define CPSW_PORT_OFFSET 0x0100
#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p)
* 0x100))
#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p)
* 0x100))
-#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) *
0x100))
-#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
-#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
-#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) *
0x100))
-#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) *
0x100))
-
-#define CPSW_CPDMA_OFFSET 0x0800
-#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
-#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
-#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
-#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
-#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
-#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
-#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
-#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
-#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
-#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
-#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
-#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
-#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
-#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
-#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
-#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
-#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
-#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
-#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
-#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
-#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
-#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) *
0x04))
-
-#define CPSW_STATS_OFFSET 0x0900
-
-#define CPSW_STATERAM_OFFSET 0x0A00
-#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) *
0x04))
-#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) *
0x04))
-#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) *
0x04))
-#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) *
0x04))
-
-#define CPSW_CPTS_OFFSET 0x0C00
-
-#define CPSW_ALE_OFFSET 0x0D00
-#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
-#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
-#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
-#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
-#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
-#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
+#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 +
((p-1) * 0x100))
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
+#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 +
((p-1) * 0x100))
+#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 +
((p-1) * 0x100))
+
+#define CPSW_CPDMA_OFFSET 0x0800
+#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
+#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
+#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
+#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
+#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
+#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
+#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
+#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
+#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
+#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
+#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
+#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
+#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
+#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
+#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
+#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 +
((p) * 0x04))
+
+#define CPSW_STATS_OFFSET 0x0900
+
+#define CPSW_STATERAM_OFFSET 0x0A00
+#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 +
((p) * 0x04))
+#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 +
((p) * 0x04))
+#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 +
((p) * 0x04))
+#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 +
((p) * 0x04))
+
+#define CPSW_CPTS_OFFSET 0x0C00
+
+#define CPSW_ALE_OFFSET 0x0D00
+#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
+#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
+#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
+#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
+#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
+#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p)
* 0x04))
/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
-#define CPSW_SL_OFFSET 0x0D80
-#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
-#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
-#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
-#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
-#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
-#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
-#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
-
-#define MDIO_OFFSET 0x1000
-#define MDIOCONTROL (MDIO_OFFSET + 0x04)
-#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
-#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
-
-#define CPSW_WR_OFFSET 0x1200
-#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
-#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
-#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
-#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
-#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
-#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
-#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
-#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
-#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
-#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
-#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
+#define CPSW_SL_OFFSET 0x0D80
+#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x04)
+#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x08)
+#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x0C)
+#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x10)
+#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x18)
+#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x1C)
+#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p))
+ 0x24)
+
+#define MDIO_OFFSET 0x1000
+#define MDIOCONTROL (MDIO_OFFSET + 0x04)
+#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
+#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
+
+#define CPSW_WR_OFFSET 0x1200
+#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
+#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
+#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
+#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x10)
+#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x14)
+#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x18)
+#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x1C)
+#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x40)
+#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x44)
+#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x48)
+#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p))
+ 0x4C)
-#define CPSW_CPPI_RAM_OFFSET 0x2000
+#define CPSW_CPPI_RAM_OFFSET 0x2000
#define CPSW_CPPI_RAM_SIZE 0x2000
#define CPSW_MEMWINDOW_SIZE 0x4000
-#define CPDMA_BD_SOP (1<<15)
-#define CPDMA_BD_EOP (1<<14)
-#define CPDMA_BD_OWNER (1<<13)
-#define CPDMA_BD_EOQ (1<<12)
-#define CPDMA_BD_TDOWNCMPLT (1<<11)
-#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
+#define CPDMA_BD_SOP (1<<15)
+#define CPDMA_BD_EOP (1<<14)
+#define CPDMA_BD_OWNER (1<<13)
+#define CPDMA_BD_EOQ (1<<12)
+#define CPDMA_BD_TDOWNCMPLT (1<<11)
+#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
struct cpsw_cpdma_bd {
volatile uint32_t next;
Modified: head/sys/arm/ti/cpsw/if_cpswvar.h
==============================================================================
--- head/sys/arm/ti/cpsw/if_cpswvar.h Thu Mar 17 04:21:57 2016
(r296979)
+++ head/sys/arm/ti/cpsw/if_cpswvar.h Thu Mar 17 06:23:48 2016
(r296980)
@@ -29,15 +29,15 @@
#ifndef _IF_CPSWVAR_H
#define _IF_CPSWVAR_H
-#define CPSW_INTR_COUNT 4
+#define CPSW_INTR_COUNT 4
/* MII BUS */
-#define CPSW_MIIBUS_RETRIES 5
-#define CPSW_MIIBUS_DELAY 1000
+#define CPSW_MIIBUS_RETRIES 5
+#define CPSW_MIIBUS_DELAY 1000
-#define CPSW_MAX_ALE_ENTRIES 1024
+#define CPSW_MAX_ALE_ENTRIES 1024
-#define CPSW_SYSCTL_COUNT 34
+#define CPSW_SYSCTL_COUNT 34
struct cpsw_slot {
uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
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