Author: andrew
Date: Tue Jul 14 12:37:47 2015
New Revision: 285537
URL: https://svnweb.freebsd.org/changeset/base/285537
Log:
Set memory to be inner-sharable. This isn't needed on device memory as the
MMU will ignore the attribute there, howeverit simplifies to code to alwas
set it.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Modified:
head/sys/arm64/arm64/locore.S
head/sys/arm64/arm64/pmap.c
head/sys/arm64/include/pte.h
Modified: head/sys/arm64/arm64/locore.S
==============================================================================
--- head/sys/arm64/arm64/locore.S Tue Jul 14 12:21:47 2015
(r285536)
+++ head/sys/arm64/arm64/locore.S Tue Jul 14 12:37:47 2015
(r285537)
@@ -469,6 +469,9 @@ build_block_pagetable:
lsl x12, x7, #2
orr x12, x12, #L2_BLOCK
orr x12, x12, #(ATTR_AF)
+#ifdef SMP
+ orr x12, x12, ATTR_SH(ATTR_SH_IS)
+#endif
/* Only use the output address bits */
lsr x9, x9, #L2_SHIFT
Modified: head/sys/arm64/arm64/pmap.c
==============================================================================
--- head/sys/arm64/arm64/pmap.c Tue Jul 14 12:21:47 2015 (r285536)
+++ head/sys/arm64/arm64/pmap.c Tue Jul 14 12:37:47 2015 (r285537)
@@ -428,8 +428,8 @@ pmap_bootstrap_dmap(vm_offset_t l1pt)
KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
pmap_load_store(&l1[l1_slot],
- (pa & ~L1_OFFSET) | ATTR_AF | L1_BLOCK |
- ATTR_IDX(CACHED_MEMORY));
+ (pa & ~L1_OFFSET) | ATTR_DEFAULT |
+ ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
}
cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE);
@@ -860,8 +860,8 @@ pmap_kenter_device(vm_offset_t sva, vm_s
while (size != 0) {
l3 = pmap_l3(kernel_pmap, va);
KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va));
- pmap_load_store(l3, (pa & ~L3_OFFSET) | ATTR_AF | L3_PAGE |
- ATTR_IDX(DEVICE_MEMORY));
+ pmap_load_store(l3, (pa & ~L3_OFFSET) | ATTR_DEFAULT |
+ ATTR_IDX(DEVICE_MEMORY) | L3_PAGE);
PTE_SYNC(l3);
va += PAGE_SIZE;
@@ -953,8 +953,8 @@ pmap_qenter(vm_offset_t sva, vm_page_t *
va = sva;
for (i = 0; i < count; i++) {
m = ma[i];
- pa = VM_PAGE_TO_PHYS(m) | ATTR_AF |
- ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RW) | L3_PAGE;
+ pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
+ ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
l3 = pmap_l3(kernel_pmap, va);
pmap_load_store(l3, pa);
PTE_SYNC(l3);
@@ -1214,8 +1214,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t
l2 = (pd_entry_t *)PHYS_TO_DMAP(*l1 & ~ATTR_MASK);
l2 = &l2[ptepindex & Ln_ADDR_MASK];
- pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | ATTR_AF |
- ATTR_IDX(CACHED_MEMORY) | L2_TABLE);
+ pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
PTE_SYNC(l2);
}
@@ -1907,14 +1906,14 @@ pmap_enter(pmap_t pmap, vm_offset_t va,
if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
VM_OBJECT_ASSERT_LOCKED(m->object);
pa = VM_PAGE_TO_PHYS(m);
- new_l3 = (pt_entry_t)(pa | ATTR_AF | L3_PAGE);
+ new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
+ L3_PAGE);
if ((prot & VM_PROT_WRITE) == 0)
new_l3 |= ATTR_AP(ATTR_AP_RO);
if ((flags & PMAP_ENTER_WIRED) != 0)
new_l3 |= ATTR_SW_WIRED;
if ((va >> 63) == 0)
new_l3 |= ATTR_AP(ATTR_AP_USER);
- new_l3 |= ATTR_IDX(m->md.pv_memattr);
CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
@@ -2243,7 +2242,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_
*/
pmap_resident_count_inc(pmap, 1);
- pa = VM_PAGE_TO_PHYS(m) | ATTR_AF | ATTR_IDX(m->md.pv_memattr) |
+ pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
ATTR_AP(ATTR_AP_RW) | L3_PAGE;
/*
Modified: head/sys/arm64/include/pte.h
==============================================================================
--- head/sys/arm64/include/pte.h Tue Jul 14 12:21:47 2015
(r285536)
+++ head/sys/arm64/include/pte.h Tue Jul 14 12:37:47 2015
(r285537)
@@ -63,6 +63,12 @@ typedef uint64_t pt_entry_t; /* page
ta
#define ATTR_IDX(x) ((x) << 2)
#define ATTR_IDX_MASK (7 << 2)
+#ifdef SMP
+#define ATTR_DEFAULT (ATTR_AF | ATTR_SH(ATTR_SH_IS))
+#else
+#define ATTR_DEFAULT (ATTR_AF)
+#endif
+
#define ATTR_DESCR_MASK 3
/* Level 0 table, 512GiB per entry */
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