Author: adrian
Date: Sat Jul 4 03:05:57 2015
New Revision: 285121
URL: https://svnweb.freebsd.org/changeset/base/285121
Log:
Reshuffle all of the DDR flush operations into a single switch/mux,
and start teaching subsystems about it.
The Atheros MIPS platforms don't guarantee any kind of FIFO consistency
with interrupts in hardware. So software needs to do a flush when it
receives an interrupt and before it calls the interrupt handler.
There are new ones for the QCA934x and QCA955x, so do a few things:
* Get rid of the individual ones (for ethernet and IP2);
* Create a mux and enum listing all the variations on DDR flushes;
* replace the uses of IP2 with the relevant one (which will typically
be "PCI" here);
* call the USB DDR flush before calling the real USB interrupt handlers;
* call the ethernet one upon receiving an interrupt that's for us,
rather than never calling it during operation.
Tested:
* QCA9558 (TP-Link archer c7 v2)
* AR9331 (Carambola 2)
TODO:
* PCI, USB, ethernet, etc need to do a double-check to see if the
interrupt was truely for them before doing the DDR. For now I
prefer "correct" over "fast".
Modified:
head/sys/mips/atheros/ar71xx_chip.c
head/sys/mips/atheros/ar71xx_cpudef.h
head/sys/mips/atheros/ar71xx_ehci.c
head/sys/mips/atheros/ar71xx_ohci.c
head/sys/mips/atheros/ar71xx_pci.c
head/sys/mips/atheros/ar724x_chip.c
head/sys/mips/atheros/ar724x_pci.c
head/sys/mips/atheros/ar91xx_chip.c
head/sys/mips/atheros/ar933x_chip.c
head/sys/mips/atheros/ar934x_chip.c
head/sys/mips/atheros/if_arge.c
head/sys/mips/atheros/qca955x_chip.c
head/sys/mips/atheros/qca955x_pci.c
Modified: head/sys/mips/atheros/ar71xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar71xx_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -254,29 +254,28 @@ ar71xx_chip_set_pll_ge(int unit, int spe
}
static void
-ar71xx_chip_ddr_flush_ge(int unit)
+ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(AR71XX_WB_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_PCIE:
+ ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid DDR flush id (%d)\n", __func__, id);
+ break;
}
}
-static void
-ar71xx_chip_ddr_flush_ip2(void)
-{
- ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
-}
-
static uint32_t
ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
{
@@ -334,8 +333,7 @@ struct ar71xx_cpu_def ar71xx_chip_def =
&ar71xx_chip_set_pll_ge,
&ar71xx_chip_set_mii_speed,
&ar71xx_chip_set_mii_if,
- &ar71xx_chip_ddr_flush_ge,
&ar71xx_chip_get_eth_pll,
- &ar71xx_chip_ddr_flush_ip2,
+ &ar71xx_chip_ddr_flush,
&ar71xx_chip_init_usb_peripheral,
};
Modified: head/sys/mips/atheros/ar71xx_cpudef.h
==============================================================================
--- head/sys/mips/atheros/ar71xx_cpudef.h Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar71xx_cpudef.h Sat Jul 4 03:05:57 2015
(r285121)
@@ -29,6 +29,16 @@
#ifndef __AR71XX_CPUDEF_H__
#define __AR71XX_CPUDEF_H__
+typedef enum {
+ AR71XX_CPU_DDR_FLUSH_GE0,
+ AR71XX_CPU_DDR_FLUSH_GE1,
+ AR71XX_CPU_DDR_FLUSH_USB,
+ AR71XX_CPU_DDR_FLUSH_PCIE,
+ AR71XX_CPU_DDR_FLUSH_WMAC,
+ AR71XX_CPU_DDR_FLUSH_PCIE_EP,
+ AR71XX_CPU_DDR_FLUSH_CHECKSUM,
+} ar71xx_flush_ddr_id_t;
+
struct ar71xx_cpu_def {
void (* detect_mem_size) (void);
void (* detect_sys_frequency) (void);
@@ -38,7 +48,6 @@ struct ar71xx_cpu_def {
void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
- void (* ar71xx_chip_ddr_flush_ge) (int);
uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
/*
@@ -51,7 +60,7 @@ struct ar71xx_cpu_def {
* This flush is done before the IRQ is handled to make
* sure the driver correctly sees any memory updates.
*/
- void (* ar71xx_chip_ddr_flush_ip2) (void);
+ void (* ar71xx_chip_ddr_flush) (ar71xx_flush_ddr_id_t id);
/*
* The USB peripheral init code is subtly different for
* each chip.
@@ -106,9 +115,9 @@ static inline void ar71xx_device_set_mii
ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
}
-static inline void ar71xx_device_flush_ddr_ge(int unit)
+static inline void ar71xx_device_flush_ddr(ar71xx_flush_ddr_id_t id)
{
- ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
+ ar71xx_cpu_ops->ar71xx_chip_ddr_flush(id);
}
static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
@@ -139,11 +148,6 @@ static inline void ar71xx_init_gmac(void
ar71xx_cpu_ops->ar71xx_chip_init_gmac();
}
-static inline void ar71xx_device_ddr_flush_ip2(void)
-{
- ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
-}
-
static inline void ar71xx_reset_nfc(int active)
{
Modified: head/sys/mips/atheros/ar71xx_ehci.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_ehci.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar71xx_ehci.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -55,6 +55,8 @@ __FBSDID("$FreeBSD$");
#include <dev/usb/controller/ehcireg.h>
#include <mips/atheros/ar71xx_setup.h>
+#include <mips/atheros/ar71xxreg.h> /* for stuff in ar71xx_cpudef.h */
+#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/atheros/ar71xx_bus_space_reversed.h>
#define EHCI_HC_DEVSTR "AR71XX Integrated USB 2.0 controller"
@@ -78,6 +80,15 @@ ar71xx_ehci_probe(device_t self)
return (BUS_PROBE_NOWILDCARD);
}
+static void
+ar71xx_ehci_intr(void *arg)
+{
+
+ /* XXX TODO: should really see if this was our interrupt.. */
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_USB);
+ ehci_interrupt(arg);
+}
+
static int
ar71xx_ehci_attach(device_t self)
{
@@ -135,7 +146,7 @@ ar71xx_ehci_attach(device_t self)
sprintf(sc->sc_vendor, "Atheros");
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
- NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
+ NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
Modified: head/sys/mips/atheros/ar71xx_ohci.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_ohci.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar71xx_ohci.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -49,6 +49,9 @@ __FBSDID("$FreeBSD$");
#include <dev/usb/controller/ohci.h>
#include <dev/usb/controller/ohcireg.h>
+#include <mips/atheros/ar71xxreg.h> /* for stuff in ar71xx_cpudef.h */
+#include <mips/atheros/ar71xx_cpudef.h>
+
static int ar71xx_ohci_attach(device_t dev);
static int ar71xx_ohci_detach(device_t dev);
static int ar71xx_ohci_probe(device_t dev);
@@ -65,6 +68,16 @@ ar71xx_ohci_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
+static void
+ar71xx_ohci_intr(void *arg)
+{
+
+ /* XXX TODO: should really see if this was our interrupt.. */
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_USB);
+ ohci_interrupt(arg);
+}
+
+
static int
ar71xx_ohci_attach(device_t dev)
{
@@ -113,7 +126,7 @@ ar71xx_ohci_attach(device_t dev)
err = bus_setup_intr(dev, sc->sc_ohci.sc_irq_res,
INTR_TYPE_BIO | INTR_MPSAFE, NULL,
- (driver_intr_t *)ohci_interrupt, sc, &sc->sc_ohci.sc_intr_hdl);
+ ar71xx_ohci_intr, sc, &sc->sc_ohci.sc_intr_hdl);
if (err) {
err = ENXIO;
goto error;
Modified: head/sys/mips/atheros/ar71xx_pci.c
==============================================================================
--- head/sys/mips/atheros/ar71xx_pci.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar71xx_pci.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -637,8 +637,8 @@ ar71xx_pci_intr(void *arg)
continue;
}
- /* Flush DDR FIFO for IP2 */
- ar71xx_device_ddr_flush_ip2();
+ /* Flush DDR FIFO for PCI/PCIe */
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
Modified: head/sys/mips/atheros/ar724x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar724x_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar724x_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -161,30 +161,28 @@ ar724x_chip_set_pll_ge(int unit, int spe
}
static void
-ar724x_chip_ddr_flush_ge(int unit)
+ar724x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_PCIE:
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid DDR flush id (%d)\n", __func__, id);
+ break;
}
}
-static void
-ar724x_chip_ddr_flush_ip2(void)
-{
-
- ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
-}
-
static uint32_t
ar724x_chip_get_eth_pll(unsigned int mac, int speed)
{
@@ -242,8 +240,7 @@ struct ar71xx_cpu_def ar724x_chip_def =
&ar724x_chip_set_pll_ge,
&ar724x_chip_set_mii_speed,
&ar71xx_chip_set_mii_if,
- &ar724x_chip_ddr_flush_ge,
&ar724x_chip_get_eth_pll,
- &ar724x_chip_ddr_flush_ip2,
+ &ar724x_chip_ddr_flush,
&ar724x_chip_init_usb_peripheral
};
Modified: head/sys/mips/atheros/ar724x_pci.c
==============================================================================
--- head/sys/mips/atheros/ar724x_pci.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar724x_pci.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -587,7 +587,6 @@ ar724x_pci_intr(void *arg)
struct intr_event *event;
uint32_t reg, irq, mask;
- ar71xx_device_ddr_flush_ip2();
reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
@@ -604,6 +603,9 @@ ar724x_pci_intr(void *arg)
return (FILTER_STRAY);
}
+ /* Flush pending memory transactions */
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
+
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
Modified: head/sys/mips/atheros/ar91xx_chip.c
==============================================================================
--- head/sys/mips/atheros/ar91xx_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar91xx_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -138,31 +138,28 @@ ar91xx_chip_set_pll_ge(int unit, int spe
}
static void
-ar91xx_chip_ddr_flush_ge(int unit)
+ar91xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_WMAC:
+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid DDR flush id (%d)\n", __func__, id);
+ break;
}
}
-static void
-ar91xx_chip_ddr_flush_ip2(void)
-{
-
- ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
-}
-
-
static uint32_t
ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
{
@@ -216,8 +213,7 @@ struct ar71xx_cpu_def ar91xx_chip_def =
&ar91xx_chip_set_pll_ge,
&ar71xx_chip_set_mii_speed,
&ar71xx_chip_set_mii_if,
- &ar91xx_chip_ddr_flush_ge,
&ar91xx_chip_get_eth_pll,
- &ar91xx_chip_ddr_flush_ip2,
+ &ar91xx_chip_ddr_flush,
&ar91xx_chip_init_usb_peripheral,
};
Modified: head/sys/mips/atheros/ar933x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar933x_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar933x_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -191,29 +191,28 @@ ar933x_chip_set_pll_ge(int unit, int spe
}
static void
-ar933x_chip_ddr_flush_ge(int unit)
+ar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_WMAC:
+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid DDR flush id (%d)\n", __func__, id);
+ break;
}
}
-static void
-ar933x_chip_ddr_flush_ip2(void)
-{
-
- ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
-}
static uint32_t
ar933x_chip_get_eth_pll(unsigned int mac, int speed)
@@ -348,9 +347,8 @@ struct ar71xx_cpu_def ar933x_chip_def =
&ar933x_chip_set_pll_ge,
&ar933x_chip_set_mii_speed,
&ar71xx_chip_set_mii_if,
- &ar933x_chip_ddr_flush_ge,
&ar933x_chip_get_eth_pll,
- &ar933x_chip_ddr_flush_ip2,
+ &ar933x_chip_ddr_flush,
&ar933x_chip_init_usb_peripheral,
NULL,
NULL,
Modified: head/sys/mips/atheros/ar934x_chip.c
==============================================================================
--- head/sys/mips/atheros/ar934x_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/ar934x_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -259,29 +259,31 @@ ar934x_chip_set_pll_ge(int unit, int spe
}
static void
-ar934x_chip_ddr_flush_ge(int unit)
+ar934x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_PCIE:
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_WMAC:
+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid DDR flush id (%d)\n", __func__, id);
+ break;
}
}
-static void
-ar934x_chip_ddr_flush_ip2(void)
-{
-
- ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
-}
static uint32_t
ar934x_chip_get_eth_pll(unsigned int mac, int speed)
@@ -457,9 +459,8 @@ struct ar71xx_cpu_def ar934x_chip_def =
&ar934x_chip_set_pll_ge,
&ar934x_chip_set_mii_speed,
&ar934x_chip_set_mii_if,
- &ar934x_chip_ddr_flush_ge,
&ar934x_chip_get_eth_pll,
- &ar934x_chip_ddr_flush_ip2,
+ &ar934x_chip_ddr_flush,
&ar934x_chip_init_usb_peripheral,
&ar934x_chip_reset_ethernet_switch,
&ar934x_chip_reset_wmac,
Modified: head/sys/mips/atheros/if_arge.c
==============================================================================
--- head/sys/mips/atheros/if_arge.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/if_arge.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -248,12 +248,25 @@ MTX_SYSINIT(miibus_mtx, &miibus_mtx, "ar
/*
* Flushes all
+ *
+ * XXX this needs to be done at interrupt time! Grr!
*/
static void
arge_flush_ddr(struct arge_softc *sc)
{
-
- ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
+ switch (sc->arge_mac_unit) {
+ case 0:
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE0);
+ break;
+ case 1:
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE1);
+ break;
+ default:
+ device_printf(sc->arge_dev, "%s: unknown unit (%d)\n",
+ __func__,
+ sc->arge_mac_unit);
+ break;
+ }
}
static int
@@ -2358,6 +2371,7 @@ arge_intr(void *arg)
}
ARGE_LOCK(sc);
+ arge_flush_ddr(sc);
if (status & DMA_INTR_RX_PKT_RCVD)
arge_rx_locked(sc);
Modified: head/sys/mips/atheros/qca955x_chip.c
==============================================================================
--- head/sys/mips/atheros/qca955x_chip.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/qca955x_chip.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -207,33 +207,36 @@ qca955x_chip_set_pll_ge(int unit, int sp
}
static void
-qca955x_chip_ddr_flush_ge(int unit)
+qca955x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
{
- switch (unit) {
- case 0:
+ switch (id) {
+ case AR71XX_CPU_DDR_FLUSH_GE0:
ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE0);
break;
- case 1:
+ case AR71XX_CPU_DDR_FLUSH_GE1:
ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_GE1);
break;
+ case AR71XX_CPU_DDR_FLUSH_USB:
+ ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_USB);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_PCIE:
+ ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_PCIE);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_WMAC:
+ ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_WMAC);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_PCIE_EP:
+ ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC1);
+ break;
+ case AR71XX_CPU_DDR_FLUSH_CHECKSUM:
+ ar71xx_ddr_flush(QCA955X_DDR_REG_FLUSH_SRC2);
+ break;
default:
- printf("%s: invalid DDR flush for arge unit: %d\n",
- __func__, unit);
- return;
+ printf("%s: invalid flush (%d)\n", __func__, id);
}
}
-/* XXX TODO: USB flush, PCIe flush, wmac flush */
-
-static void
-qca955x_chip_ddr_flush_ip2(void)
-{
-#if 0
- ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
-#endif
-}
-
static uint32_t
qca955x_chip_get_eth_pll(unsigned int mac, int speed)
{
@@ -388,9 +391,8 @@ struct ar71xx_cpu_def qca955x_chip_def =
&qca955x_chip_set_pll_ge,
&qca955x_chip_set_mii_speed,
&qca955x_chip_set_mii_if,
- &qca955x_chip_ddr_flush_ge,
&qca955x_chip_get_eth_pll,
- &qca955x_chip_ddr_flush_ip2,
+ &qca955x_chip_ddr_flush,
&qca955x_chip_init_usb_peripheral,
&qca955x_chip_reset_ethernet_switch,
&qca955x_chip_reset_wmac,
Modified: head/sys/mips/atheros/qca955x_pci.c
==============================================================================
--- head/sys/mips/atheros/qca955x_pci.c Sat Jul 4 02:59:30 2015
(r285120)
+++ head/sys/mips/atheros/qca955x_pci.c Sat Jul 4 03:05:57 2015
(r285121)
@@ -525,11 +525,12 @@ qca955x_pci_intr(void *arg)
struct intr_event *event;
uint32_t reg, irq, mask;
- /* XXX TODO - may need to flush a different handler? */
- ar71xx_device_ddr_flush_ip2();
+ /* There's only one PCIe DDR flush for both PCIe EPs */
+ ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE);
reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS);
mask = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);
+
/*
* Handle only unmasked interrupts
*/
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