Author: np
Date: Tue Jun 30 22:30:21 2015
New Revision: 284984
URL: https://svnweb.freebsd.org/changeset/base/284984
Log:
cxgbetool: fix code that decodes T5 SGE contexts. Some of the fields
that changed between T4 and T5 were not displayed correctly.
Obtained from: Chelsio
MFC after: 3 days
Differential Revision:
Modified:
head/tools/tools/cxgbetool/cxgbetool.c
Modified: head/tools/tools/cxgbetool/cxgbetool.c
==============================================================================
--- head/tools/tools/cxgbetool/cxgbetool.c Tue Jun 30 21:19:27 2015
(r284983)
+++ head/tools/tools/cxgbetool/cxgbetool.c Tue Jun 30 22:30:21 2015
(r284984)
@@ -1245,9 +1245,159 @@ show_struct(const uint32_t *words, int n
#define FIELD1(name, start) FIELD(name, start, start)
static void
-show_sge_context(const struct t4_sge_context *p)
+show_t5_ctxt(const struct t4_sge_context *p)
{
- static struct field_desc egress[] = {
+ static struct field_desc egress_t5[] = {
+ FIELD("DCA_ST:", 181, 191),
+ FIELD1("StatusPgNS:", 180),
+ FIELD1("StatusPgRO:", 179),
+ FIELD1("FetchNS:", 178),
+ FIELD1("FetchRO:", 177),
+ FIELD1("Valid:", 176),
+ FIELD("PCIeDataChannel:", 174, 175),
+ FIELD1("StatusPgTPHintEn:", 173),
+ FIELD("StatusPgTPHint:", 171, 172),
+ FIELD1("FetchTPHintEn:", 170),
+ FIELD("FetchTPHint:", 168, 169),
+ FIELD1("FCThreshOverride:", 167),
+ { "WRLength:", 162, 166, 9, 0, 1 },
+ FIELD1("WRLengthKnown:", 161),
+ FIELD1("ReschedulePending:", 160),
+ FIELD1("OnChipQueue:", 159),
+ FIELD1("FetchSizeMode:", 158),
+ { "FetchBurstMin:", 156, 157, 4, 0, 1 },
+ FIELD1("FLMPacking:", 155),
+ FIELD("FetchBurstMax:", 153, 154),
+ FIELD("uPToken:", 133, 152),
+ FIELD1("uPTokenEn:", 132),
+ FIELD1("UserModeIO:", 131),
+ FIELD("uPFLCredits:", 123, 130),
+ FIELD1("uPFLCreditEn:", 122),
+ FIELD("FID:", 111, 121),
+ FIELD("HostFCMode:", 109, 110),
+ FIELD1("HostFCOwner:", 108),
+ { "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
+ FIELD("CIDX:", 89, 104),
+ FIELD("PIDX:", 73, 88),
+ { "BaseAddress:", 18, 72, 9, 1 },
+ FIELD("QueueSize:", 2, 17),
+ FIELD1("QueueType:", 1),
+ FIELD1("CachePriority:", 0),
+ { NULL }
+ };
+ static struct field_desc fl_t5[] = {
+ FIELD("DCA_ST:", 181, 191),
+ FIELD1("StatusPgNS:", 180),
+ FIELD1("StatusPgRO:", 179),
+ FIELD1("FetchNS:", 178),
+ FIELD1("FetchRO:", 177),
+ FIELD1("Valid:", 176),
+ FIELD("PCIeDataChannel:", 174, 175),
+ FIELD1("StatusPgTPHintEn:", 173),
+ FIELD("StatusPgTPHint:", 171, 172),
+ FIELD1("FetchTPHintEn:", 170),
+ FIELD("FetchTPHint:", 168, 169),
+ FIELD1("FCThreshOverride:", 167),
+ FIELD1("ReschedulePending:", 160),
+ FIELD1("OnChipQueue:", 159),
+ FIELD1("FetchSizeMode:", 158),
+ { "FetchBurstMin:", 156, 157, 4, 0, 1 },
+ FIELD1("FLMPacking:", 155),
+ FIELD("FetchBurstMax:", 153, 154),
+ FIELD1("FLMcongMode:", 152),
+ FIELD("MaxuPFLCredits:", 144, 151),
+ FIELD("FLMcontextID:", 133, 143),
+ FIELD1("uPTokenEn:", 132),
+ FIELD1("UserModeIO:", 131),
+ FIELD("uPFLCredits:", 123, 130),
+ FIELD1("uPFLCreditEn:", 122),
+ FIELD("FID:", 111, 121),
+ FIELD("HostFCMode:", 109, 110),
+ FIELD1("HostFCOwner:", 108),
+ { "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
+ FIELD("CIDX:", 89, 104),
+ FIELD("PIDX:", 73, 88),
+ { "BaseAddress:", 18, 72, 9, 1 },
+ FIELD("QueueSize:", 2, 17),
+ FIELD1("QueueType:", 1),
+ FIELD1("CachePriority:", 0),
+ { NULL }
+ };
+ static struct field_desc ingress_t5[] = {
+ FIELD("DCA_ST:", 143, 153),
+ FIELD1("ISCSICoalescing:", 142),
+ FIELD1("Queue_Valid:", 141),
+ FIELD1("TimerPending:", 140),
+ FIELD1("DropRSS:", 139),
+ FIELD("PCIeChannel:", 137, 138),
+ FIELD1("SEInterruptArmed:", 136),
+ FIELD1("CongestionMgtEnable:", 135),
+ FIELD1("NoSnoop:", 134),
+ FIELD1("RelaxedOrdering:", 133),
+ FIELD1("GTSmode:", 132),
+ FIELD1("TPHintEn:", 131),
+ FIELD("TPHint:", 129, 130),
+ FIELD1("UpdateScheduling:", 128),
+ FIELD("UpdateDelivery:", 126, 127),
+ FIELD1("InterruptSent:", 125),
+ FIELD("InterruptIDX:", 114, 124),
+ FIELD1("InterruptDestination:", 113),
+ FIELD1("InterruptArmed:", 112),
+ FIELD("RxIntCounter:", 106, 111),
+ FIELD("RxIntCounterThreshold:", 104, 105),
+ FIELD1("Generation:", 103),
+ { "BaseAddress:", 48, 102, 9, 1 },
+ FIELD("PIDX:", 32, 47),
+ FIELD("CIDX:", 16, 31),
+ { "QueueSize:", 4, 15, 4, 0 },
+ { "QueueEntrySize:", 2, 3, 4, 0, 1 },
+ FIELD1("QueueEntryOverride:", 1),
+ FIELD1("CachePriority:", 0),
+ { NULL }
+ };
+ static struct field_desc flm_t5[] = {
+ FIELD1("Valid:", 89),
+ FIELD("SplitLenMode:", 87, 88),
+ FIELD1("TPHintEn:", 86),
+ FIELD("TPHint:", 84, 85),
+ FIELD1("NoSnoop:", 83),
+ FIELD1("RelaxedOrdering:", 82),
+ FIELD("DCA_ST:", 71, 81),
+ FIELD("EQid:", 54, 70),
+ FIELD("SplitEn:", 52, 53),
+ FIELD1("PadEn:", 51),
+ FIELD1("PackEn:", 50),
+ FIELD1("Cache_Lock :", 49),
+ FIELD1("CongDrop:", 48),
+ FIELD("PackOffset:", 16, 47),
+ FIELD("CIDX:", 8, 15),
+ FIELD("PIDX:", 0, 7),
+ { NULL }
+ };
+ static struct field_desc conm_t5[] = {
+ FIELD1("CngMPSEnable:", 21),
+ FIELD("CngTPMode:", 19, 20),
+ FIELD1("CngDBPHdr:", 18),
+ FIELD1("CngDBPData:", 17),
+ FIELD1("CngIMSG:", 16),
+ { "CngChMap:", 0, 15, 0, 1, 0 },
+ { NULL }
+ };
+
+ if (p->mem_id == SGE_CONTEXT_EGRESS)
+ show_struct(p->data, 6, (p->data[0] & 2) ? fl_t5 : egress_t5);
+ else if (p->mem_id == SGE_CONTEXT_FLM)
+ show_struct(p->data, 3, flm_t5);
+ else if (p->mem_id == SGE_CONTEXT_INGRESS)
+ show_struct(p->data, 5, ingress_t5);
+ else if (p->mem_id == SGE_CONTEXT_CNM)
+ show_struct(p->data, 1, conm_t5);
+}
+
+static void
+show_t4_ctxt(const struct t4_sge_context *p)
+{
+ static struct field_desc egress_t4[] = {
FIELD1("StatusPgNS:", 180),
FIELD1("StatusPgRO:", 179),
FIELD1("FetchNS:", 178),
@@ -1281,7 +1431,7 @@ show_sge_context(const struct t4_sge_con
FIELD1("CachePriority:", 0),
{ NULL }
};
- static struct field_desc fl[] = {
+ static struct field_desc fl_t4[] = {
FIELD1("StatusPgNS:", 180),
FIELD1("StatusPgRO:", 179),
FIELD1("FetchNS:", 178),
@@ -1291,8 +1441,6 @@ show_sge_context(const struct t4_sge_con
FIELD1("DCAEgrQEn:", 173),
FIELD("DCACPUID:", 168, 172),
FIELD1("FCThreshOverride:", 167),
- FIELD("WRLength:", 162, 166),
- FIELD1("WRLengthKnown:", 161),
FIELD1("ReschedulePending:", 160),
FIELD1("OnChipQueue:", 159),
FIELD1("FetchSizeMode", 158),
@@ -1317,7 +1465,7 @@ show_sge_context(const struct t4_sge_con
FIELD1("CachePriority:", 0),
{ NULL }
};
- static struct field_desc ingress[] = {
+ static struct field_desc ingress_t4[] = {
FIELD1("NoSnoop:", 145),
FIELD1("RelaxedOrdering:", 144),
FIELD1("GTSmode:", 143),
@@ -1348,7 +1496,7 @@ show_sge_context(const struct t4_sge_con
FIELD1("CachePriority:", 0),
{ NULL }
};
- static struct field_desc flm[] = {
+ static struct field_desc flm_t4[] = {
FIELD1("NoSnoop:", 79),
FIELD1("RelaxedOrdering:", 78),
FIELD1("Valid:", 77),
@@ -1364,31 +1512,22 @@ show_sge_context(const struct t4_sge_con
FIELD("PIDX:", 0, 7),
{ NULL }
};
- static struct field_desc conm[] = {
+ static struct field_desc conm_t4[] = {
FIELD1("CngDBPHdr:", 6),
FIELD1("CngDBPData:", 5),
FIELD1("CngIMSG:", 4),
{ "CngChMap:", 0, 3, 0, 1, 0},
{ NULL }
};
- static struct field_desc t5_conm[] = {
- FIELD1("CngMPSEnable:", 21),
- FIELD("CngTPMode:", 19, 20),
- FIELD1("CngDBPHdr:", 18),
- FIELD1("CngDBPData:", 17),
- FIELD1("CngIMSG:", 16),
- { "CngChMap:", 0, 15, 0, 1, 0},
- { NULL }
- };
if (p->mem_id == SGE_CONTEXT_EGRESS)
- show_struct(p->data, 6, (p->data[0] & 2) ? fl : egress);
+ show_struct(p->data, 6, (p->data[0] & 2) ? fl_t4 : egress_t4);
else if (p->mem_id == SGE_CONTEXT_FLM)
- show_struct(p->data, 3, flm);
+ show_struct(p->data, 3, flm_t4);
else if (p->mem_id == SGE_CONTEXT_INGRESS)
- show_struct(p->data, 5, ingress);
+ show_struct(p->data, 5, ingress_t4);
else if (p->mem_id == SGE_CONTEXT_CNM)
- show_struct(p->data, 1, chip_id == 5 ? t5_conm : conm);
+ show_struct(p->data, 1, conm_t4);
}
#undef FIELD
@@ -1432,7 +1571,11 @@ get_sge_context(int argc, const char *ar
if (rc != 0)
return (rc);
- show_sge_context(&cntxt);
+ if (chip_id == 4)
+ show_t4_ctxt(&cntxt);
+ else
+ show_t5_ctxt(&cntxt);
+
return (0);
}
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