Author: imp
Date: Tue Nov 18 01:39:21 2014
New Revision: 274639
URL: https://svnweb.freebsd.org/changeset/base/274639
Log:
Modernize comments about BIOSes being lame since in this detail they
aren't lame, the rules changed along the way. Catch up to 1999 or so
with the new rules.
Modified:
head/sys/dev/pccbb/pccbb.c
Modified: head/sys/dev/pccbb/pccbb.c
==============================================================================
--- head/sys/dev/pccbb/pccbb.c Tue Nov 18 01:38:39 2014 (r274638)
+++ head/sys/dev/pccbb/pccbb.c Tue Nov 18 01:39:21 2014 (r274639)
@@ -1584,13 +1584,17 @@ cbb_resume(device_t self)
uint32_t tmp;
/*
- * Some BIOSes will not save the BARs for the pci chips, so we
- * must do it ourselves. If the BAR is reset to 0 for an I/O
- * device, it will read back as 0x1, so no explicit test for
- * memory devices are needed.
+ * In the APM and early ACPI era, BIOSes saved the PCI config
+ * registers. As chips became more complicated, that functionality moved
+ * into the ACPI code / tables. We must therefore, restore the settings
+ * we made here to make sure the device come back. Transitions to Dx
+ * from D0 and back to D0 cause the bridge to lose its config space, so
+ * all the bus mappings and such are preserved.
*
- * Note: The PCI bus code should do this automatically for us on
- * suspend/resume, but until it does, we have to cope.
+ * For most drivers, the PCI layer handles this saving. However,
+ * sicne there's much black magic and archane art hidden in these
+ * few lines of code that would be difficult to transition into
+ * the PCI layer.
*/
pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4);
DEVPRINTF((self, "PCI Memory allocated: %08lx\n",
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