Author: jhb
Date: Thu Sep 4 14:26:25 2014
New Revision: 271098
URL: http://svnweb.freebsd.org/changeset/base/271098
Log:
Merge the amd64 and i386 identcpu.c into a single x86 implementation.
This brings the structured extended features mask and VT-x reporting to
i386 and Intel cache and TLB info (under bootverbose) to amd64.
Added:
head/sys/x86/x86/identcpu.c
- copied, changed from r271083, head/sys/amd64/amd64/identcpu.c
Deleted:
head/sys/amd64/amd64/identcpu.c
head/sys/i386/i386/identcpu.c
Modified:
head/sys/conf/files.amd64
head/sys/conf/files.i386
head/sys/conf/files.pc98
head/sys/i386/i386/initcpu.c
head/sys/i386/include/md_var.h
Modified: head/sys/conf/files.amd64
==============================================================================
--- head/sys/conf/files.amd64 Thu Sep 4 14:25:32 2014 (r271097)
+++ head/sys/conf/files.amd64 Thu Sep 4 14:26:25 2014 (r271098)
@@ -103,7 +103,6 @@ amd64/amd64/elf_machdep.c standard
amd64/amd64/exception.S standard
amd64/amd64/fpu.c standard
amd64/amd64/gdb_machdep.c optional gdb
-amd64/amd64/identcpu.c standard
amd64/amd64/in_cksum.c optional inet | inet6
amd64/amd64/initcpu.c standard
amd64/amd64/io.c optional io
@@ -542,6 +541,7 @@ x86/x86/busdma_bounce.c standard
x86/x86/busdma_machdep.c standard
x86/x86/dump_machdep.c standard
x86/x86/fdt_machdep.c optional fdt
+x86/x86/identcpu.c standard
x86/x86/intr_machdep.c standard
x86/x86/io_apic.c standard
x86/x86/legacy.c standard
Modified: head/sys/conf/files.i386
==============================================================================
--- head/sys/conf/files.i386 Thu Sep 4 14:25:32 2014 (r271097)
+++ head/sys/conf/files.i386 Thu Sep 4 14:26:25 2014 (r271098)
@@ -443,7 +443,6 @@ i386/xen/exception.s optional xen
i386/i386/gdb_machdep.c optional gdb
i386/i386/geode.c optional cpu_geode
i386/i386/i686_mem.c optional mem
-i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet | inet6
i386/i386/initcpu.c standard
i386/i386/io.c optional io
@@ -581,6 +580,7 @@ x86/x86/busdma_bounce.c standard
x86/x86/busdma_machdep.c standard
x86/x86/dump_machdep.c standard
x86/x86/fdt_machdep.c optional fdt
+x86/x86/identcpu.c standard
x86/x86/intr_machdep.c standard
x86/x86/io_apic.c optional apic
x86/x86/legacy.c optional native
Modified: head/sys/conf/files.pc98
==============================================================================
--- head/sys/conf/files.pc98 Thu Sep 4 14:25:32 2014 (r271097)
+++ head/sys/conf/files.pc98 Thu Sep 4 14:26:25 2014 (r271098)
@@ -140,7 +140,6 @@ i386/i386/elf_machdep.c standard
i386/i386/exception.s standard
i386/i386/gdb_machdep.c optional gdb
i386/i386/i686_mem.c optional mem
-i386/i386/identcpu.c standard
i386/i386/in_cksum.c optional inet | inet6
i386/i386/initcpu.c standard
i386/i386/io.c optional io
@@ -248,6 +247,7 @@ x86/pci/pci_bus.c optional pci
x86/x86/busdma_bounce.c standard
x86/x86/busdma_machdep.c standard
x86/x86/dump_machdep.c standard
+x86/x86/identcpu.c standard
x86/x86/intr_machdep.c standard
x86/x86/io_apic.c optional apic
x86/x86/legacy.c standard
Modified: head/sys/i386/i386/initcpu.c
==============================================================================
--- head/sys/i386/i386/initcpu.c Thu Sep 4 14:25:32 2014
(r271097)
+++ head/sys/i386/i386/initcpu.c Thu Sep 4 14:26:25 2014
(r271098)
@@ -95,6 +95,7 @@ u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
#endif
u_int cpu_clflush_line_size = 32;
+u_int cpu_stdext_feature;
u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
Modified: head/sys/i386/include/md_var.h
==============================================================================
--- head/sys/i386/include/md_var.h Thu Sep 4 14:25:32 2014
(r271097)
+++ head/sys/i386/include/md_var.h Thu Sep 4 14:26:25 2014
(r271098)
@@ -48,6 +48,7 @@ extern u_int amd_pminfo;
extern u_int via_feature_rng;
extern u_int via_feature_xcrypt;
extern u_int cpu_clflush_line_size;
+extern u_int cpu_stdext_feature;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
Copied and modified: head/sys/x86/x86/identcpu.c (from r271083,
head/sys/amd64/amd64/identcpu.c)
==============================================================================
--- head/sys/amd64/amd64/identcpu.c Thu Sep 4 02:28:17 2014
(r271083, copy source)
+++ head/sys/x86/x86/identcpu.c Thu Sep 4 14:26:25 2014 (r271098)
@@ -57,21 +57,32 @@ __FBSDID("$FreeBSD$");
#include <machine/cputypes.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
+#include <machine/md_var.h>
#include <machine/segments.h>
#include <machine/specialreg.h>
-#include <machine/md_var.h>
#include <amd64/vmm/intel/vmx_controls.h>
#include <x86/isa/icu.h>
+#ifdef __i386__
+#define IDENTBLUE_CYRIX486 0
+#define IDENTBLUE_IBMCPU 1
+#define IDENTBLUE_CYRIXM2 2
+
+static void identifycyrix(void);
+static void print_transmeta_info(void);
+#endif
static u_int find_cpu_vendor_id(void);
static void print_AMD_info(void);
+static void print_INTEL_info(void);
+static void print_INTEL_TLB(u_int data);
static void print_via_padlock_info(void);
static void print_vmx_info(void);
int cpu_class;
-char machine[] = "amd64";
+char machine[] = MACHINE;
+#ifdef __amd64__
#ifdef SCTL_MASK32
extern int adaptive_machine_arch;
#endif
@@ -95,6 +106,10 @@ sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
}
SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
NULL, 0, sysctl_hw_machine, "A", "Machine class");
+#else
+SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
+ machine, 0, "Machine class");
+#endif
static char cpu_model[128];
SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
@@ -108,12 +123,48 @@ static eventhandler_tag tsc_post_tag;
static char cpu_brand[48];
+#ifdef __i386__
+#define MAX_BRAND_INDEX 8
+
+static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
+ NULL, /* No brand */
+ "Intel Celeron",
+ "Intel Pentium III",
+ "Intel Pentium III Xeon",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "Intel Pentium 4"
+};
+#endif
+
static struct {
char *cpu_name;
int cpu_class;
-} amd64_cpus[] = {
+} cpus[] = {
+#ifdef __i386__
+ { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
+ { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
+ { "i386DX", CPUCLASS_386 }, /* CPU_386 */
+ { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
+ { "i486DX", CPUCLASS_486 }, /* CPU_486 */
+ { "Pentium", CPUCLASS_586 }, /* CPU_586 */
+ { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
+ { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
+ { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
+ { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
+ { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
+ { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
+ { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
+ { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
+ { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
+ { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
+ { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
+#else
{ "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
{ "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
+#endif
};
static struct {
@@ -123,18 +174,30 @@ static struct {
{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
{ CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
+#ifdef __i386__
+ { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
+ { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
+ { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
+ { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
+ { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
+ { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
+ { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
+#if 0
+ /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
+ { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
+#endif
+#endif
};
-
void
printcpuinfo(void)
{
u_int regs[4], i;
char *brand;
- cpu_class = amd64_cpus[cpu].cpu_class;
+ cpu_class = cpus[cpu].cpu_class;
printf("CPU: ");
- strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
+ strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
/* Check for extended CPUID information and a processor name. */
if (cpu_exthigh >= 0x80000004) {
@@ -148,8 +211,143 @@ printcpuinfo(void)
switch (cpu_vendor_id) {
case CPU_VENDOR_INTEL:
+#ifdef __i386__
+ if ((cpu_id & 0xf00) > 0x300) {
+ u_int brand_index;
+
+ cpu_model[0] = '\0';
+
+ switch (cpu_id & 0x3000) {
+ case 0x1000:
+ strcpy(cpu_model, "Overdrive ");
+ break;
+ case 0x2000:
+ strcpy(cpu_model, "Dual ");
+ break;
+ }
+
+ switch (cpu_id & 0xf00) {
+ case 0x400:
+ strcat(cpu_model, "i486 ");
+ /* Check the particular flavor of 486 */
+ switch (cpu_id & 0xf0) {
+ case 0x00:
+ case 0x10:
+ strcat(cpu_model, "DX");
+ break;
+ case 0x20:
+ strcat(cpu_model, "SX");
+ break;
+ case 0x30:
+ strcat(cpu_model, "DX2");
+ break;
+ case 0x40:
+ strcat(cpu_model, "SL");
+ break;
+ case 0x50:
+ strcat(cpu_model, "SX2");
+ break;
+ case 0x70:
+ strcat(cpu_model,
+ "DX2 Write-Back Enhanced");
+ break;
+ case 0x80:
+ strcat(cpu_model, "DX4");
+ break;
+ }
+ break;
+ case 0x500:
+ /* Check the particular flavor of 586 */
+ strcat(cpu_model, "Pentium");
+ switch (cpu_id & 0xf0) {
+ case 0x00:
+ strcat(cpu_model, " A-step");
+ break;
+ case 0x10:
+ strcat(cpu_model, "/P5");
+ break;
+ case 0x20:
+ strcat(cpu_model, "/P54C");
+ break;
+ case 0x30:
+ strcat(cpu_model, "/P24T");
+ break;
+ case 0x40:
+ strcat(cpu_model, "/P55C");
+ break;
+ case 0x70:
+ strcat(cpu_model, "/P54C");
+ break;
+ case 0x80:
+ strcat(cpu_model, "/P55C
(quarter-micron)");
+ break;
+ default:
+ /* nothing */
+ break;
+ }
+#if defined(I586_CPU) && !defined(NO_F00F_HACK)
+ /*
+ * XXX - If/when Intel fixes the bug, this
+ * should also check the version of the
+ * CPU, not just that it's a Pentium.
+ */
+ has_f00f_bug = 1;
+#endif
+ break;
+ case 0x600:
+ /* Check the particular flavor of 686 */
+ switch (cpu_id & 0xf0) {
+ case 0x00:
+ strcat(cpu_model, "Pentium Pro A-step");
+ break;
+ case 0x10:
+ strcat(cpu_model, "Pentium Pro");
+ break;
+ case 0x30:
+ case 0x50:
+ case 0x60:
+ strcat(cpu_model,
+ "Pentium II/Pentium II Xeon/Celeron");
+ cpu = CPU_PII;
+ break;
+ case 0x70:
+ case 0x80:
+ case 0xa0:
+ case 0xb0:
+ strcat(cpu_model,
+ "Pentium III/Pentium III Xeon/Celeron");
+ cpu = CPU_PIII;
+ break;
+ default:
+ strcat(cpu_model, "Unknown 80686");
+ break;
+ }
+ break;
+ case 0xf00:
+ strcat(cpu_model, "Pentium 4");
+ cpu = CPU_P4;
+ break;
+ default:
+ strcat(cpu_model, "unknown");
+ break;
+ }
+
+ /*
+ * If we didn't get a brand name from the extended
+ * CPUID, try to look it up in the brand table.
+ */
+ if (cpu_high > 0 && *cpu_brand == '\0') {
+ brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
+ if (brand_index <= MAX_BRAND_INDEX &&
+ cpu_brandtable[brand_index] != NULL)
+ strcpy(cpu_brand,
+ cpu_brandtable[brand_index]);
+ }
+ }
+#else
/* Please make up your mind folks! */
strcat(cpu_model, "EM64T");
+#endif
break;
case CPU_VENDOR_AMD:
/*
@@ -158,18 +356,297 @@ printcpuinfo(void)
* (also describes ``Features'' encodings.
*/
strcpy(cpu_model, "AMD ");
+#ifdef __i386__
+ switch (cpu_id & 0xFF0) {
+ case 0x410:
+ strcat(cpu_model, "Standard Am486DX");
+ break;
+ case 0x430:
+ strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
+ break;
+ case 0x470:
+ strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
+ break;
+ case 0x480:
+ strcat(cpu_model, "Enhanced Am486DX4/Am5x86
Write-Through");
+ break;
+ case 0x490:
+ strcat(cpu_model, "Enhanced Am486DX4/Am5x86
Write-Back");
+ break;
+ case 0x4E0:
+ strcat(cpu_model, "Am5x86 Write-Through");
+ break;
+ case 0x4F0:
+ strcat(cpu_model, "Am5x86 Write-Back");
+ break;
+ case 0x500:
+ strcat(cpu_model, "K5 model 0");
+ break;
+ case 0x510:
+ strcat(cpu_model, "K5 model 1");
+ break;
+ case 0x520:
+ strcat(cpu_model, "K5 PR166 (model 2)");
+ break;
+ case 0x530:
+ strcat(cpu_model, "K5 PR200 (model 3)");
+ break;
+ case 0x560:
+ strcat(cpu_model, "K6");
+ break;
+ case 0x570:
+ strcat(cpu_model, "K6 266 (model 1)");
+ break;
+ case 0x580:
+ strcat(cpu_model, "K6-2");
+ break;
+ case 0x590:
+ strcat(cpu_model, "K6-III");
+ break;
+ case 0x5a0:
+ strcat(cpu_model, "Geode LX");
+ /*
+ * Make sure the TSC runs through suspension,
+ * otherwise we can't use it as timecounter
+ */
+ wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ break;
+ }
+#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
+ if ((cpu_id & 0xf00) == 0x500) {
+ if (((cpu_id & 0x0f0) > 0)
+ && ((cpu_id & 0x0f0) < 0x60)
+ && ((cpu_id & 0x00f) > 3))
+ enable_K5_wt_alloc();
+ else if (((cpu_id & 0x0f0) > 0x80)
+ || (((cpu_id & 0x0f0) == 0x80)
+ && (cpu_id & 0x00f) > 0x07))
+ enable_K6_2_wt_alloc();
+ else if ((cpu_id & 0x0f0) > 0x50)
+ enable_K6_wt_alloc();
+ }
+#endif
+#else
if ((cpu_id & 0xf00) == 0xf00)
strcat(cpu_model, "AMD64 Processor");
else
strcat(cpu_model, "Unknown");
+#endif
+ break;
+#ifdef __i386__
+ case CPU_VENDOR_CYRIX:
+ strcpy(cpu_model, "Cyrix ");
+ switch (cpu_id & 0xff0) {
+ case 0x440:
+ strcat(cpu_model, "MediaGX");
+ break;
+ case 0x520:
+ strcat(cpu_model, "6x86");
+ break;
+ case 0x540:
+ cpu_class = CPUCLASS_586;
+ strcat(cpu_model, "GXm");
+ break;
+ case 0x600:
+ strcat(cpu_model, "6x86MX");
+ break;
+ default:
+ /*
+ * Even though CPU supports the cpuid
+ * instruction, it can be disabled.
+ * Therefore, this routine supports all Cyrix
+ * CPUs.
+ */
+ switch (cyrix_did & 0xf0) {
+ case 0x00:
+ switch (cyrix_did & 0x0f) {
+ case 0x00:
+ strcat(cpu_model, "486SLC");
+ break;
+ case 0x01:
+ strcat(cpu_model, "486DLC");
+ break;
+ case 0x02:
+ strcat(cpu_model, "486SLC2");
+ break;
+ case 0x03:
+ strcat(cpu_model, "486DLC2");
+ break;
+ case 0x04:
+ strcat(cpu_model, "486SRx");
+ break;
+ case 0x05:
+ strcat(cpu_model, "486DRx");
+ break;
+ case 0x06:
+ strcat(cpu_model, "486SRx2");
+ break;
+ case 0x07:
+ strcat(cpu_model, "486DRx2");
+ break;
+ case 0x08:
+ strcat(cpu_model, "486SRu");
+ break;
+ case 0x09:
+ strcat(cpu_model, "486DRu");
+ break;
+ case 0x0a:
+ strcat(cpu_model, "486SRu2");
+ break;
+ case 0x0b:
+ strcat(cpu_model, "486DRu2");
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ break;
+ }
+ break;
+ case 0x10:
+ switch (cyrix_did & 0x0f) {
+ case 0x00:
+ strcat(cpu_model, "486S");
+ break;
+ case 0x01:
+ strcat(cpu_model, "486S2");
+ break;
+ case 0x02:
+ strcat(cpu_model, "486Se");
+ break;
+ case 0x03:
+ strcat(cpu_model, "486S2e");
+ break;
+ case 0x0a:
+ strcat(cpu_model, "486DX");
+ break;
+ case 0x0b:
+ strcat(cpu_model, "486DX2");
+ break;
+ case 0x0f:
+ strcat(cpu_model, "486DX4");
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ break;
+ }
+ break;
+ case 0x20:
+ if ((cyrix_did & 0x0f) < 8)
+ strcat(cpu_model, "6x86"); /*
Where did you get it? */
+ else
+ strcat(cpu_model, "5x86");
+ break;
+ case 0x30:
+ strcat(cpu_model, "6x86");
+ break;
+ case 0x40:
+ if ((cyrix_did & 0xf000) == 0x3000) {
+ cpu_class = CPUCLASS_586;
+ strcat(cpu_model, "GXm");
+ } else
+ strcat(cpu_model, "MediaGX");
+ break;
+ case 0x50:
+ strcat(cpu_model, "6x86MX");
+ break;
+ case 0xf0:
+ switch (cyrix_did & 0x0f) {
+ case 0x0d:
+ strcat(cpu_model, "Overdrive CPU");
+ break;
+ case 0x0e:
+ strcpy(cpu_model, "Texas Instruments
486SXL");
+ break;
+ case 0x0f:
+ strcat(cpu_model, "486SLC/DLC");
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ break;
+ }
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ break;
+ }
+ break;
+ }
+ break;
+ case CPU_VENDOR_RISE:
+ strcpy(cpu_model, "Rise ");
+ switch (cpu_id & 0xff0) {
+ case 0x500: /* 6401 and 6441 (Kirin) */
+ case 0x520: /* 6510 (Lynx) */
+ strcat(cpu_model, "mP6");
+ break;
+ default:
+ strcat(cpu_model, "Unknown");
+ }
break;
+#endif
case CPU_VENDOR_CENTAUR:
+#ifdef __i386__
+ switch (cpu_id & 0xff0) {
+ case 0x540:
+ strcpy(cpu_model, "IDT WinChip C6");
+ break;
+ case 0x580:
+ strcpy(cpu_model, "IDT WinChip 2");
+ break;
+ case 0x590:
+ strcpy(cpu_model, "IDT WinChip 3");
+ break;
+ case 0x660:
+ strcpy(cpu_model, "VIA C3 Samuel");
+ break;
+ case 0x670:
+ if (cpu_id & 0x8)
+ strcpy(cpu_model, "VIA C3 Ezra");
+ else
+ strcpy(cpu_model, "VIA C3 Samuel 2");
+ break;
+ case 0x680:
+ strcpy(cpu_model, "VIA C3 Ezra-T");
+ break;
+ case 0x690:
+ strcpy(cpu_model, "VIA C3 Nehemiah");
+ break;
+ case 0x6a0:
+ case 0x6d0:
+ strcpy(cpu_model, "VIA C7 Esther");
+ break;
+ case 0x6f0:
+ strcpy(cpu_model, "VIA Nano");
+ break;
+ default:
+ strcpy(cpu_model, "VIA/IDT Unknown");
+ }
+#else
strcpy(cpu_model, "VIA ");
if ((cpu_id & 0xff0) == 0x6f0)
strcat(cpu_model, "Nano Processor");
else
strcat(cpu_model, "Unknown");
+#endif
+ break;
+#ifdef __i386__
+ case CPU_VENDOR_IBM:
+ strcpy(cpu_model, "Blue Lightning CPU");
break;
+ case CPU_VENDOR_NSC:
+ switch (cpu_id & 0xff0) {
+ case 0x540:
+ strcpy(cpu_model, "Geode SC1100");
+ cpu = CPU_GEODE1100;
+ break;
+ default:
+ strcpy(cpu_model, "Geode/NSC unknown");
+ break;
+ }
+ break;
+#endif
default:
strcat(cpu_model, "Unknown");
break;
@@ -186,16 +663,40 @@ printcpuinfo(void)
strcpy(cpu_model, brand);
printf("%s (", cpu_model);
+ if (tsc_freq != 0) {
+ hw_clockrate = (tsc_freq + 5000) / 1000000;
+ printf("%jd.%02d-MHz ",
+ (intmax_t)(tsc_freq + 4999) / 1000000,
+ (u_int)((tsc_freq + 4999) / 10000) % 100);
+ }
switch(cpu_class) {
+#ifdef __i386__
+ case CPUCLASS_286:
+ printf("286");
+ break;
+ case CPUCLASS_386:
+ printf("386");
+ break;
+#if defined(I486_CPU)
+ case CPUCLASS_486:
+ printf("486");
+ break;
+#endif
+#if defined(I586_CPU)
+ case CPUCLASS_586:
+ printf("586");
+ break;
+#endif
+#if defined(I686_CPU)
+ case CPUCLASS_686:
+ printf("686");
+ break;
+#endif
+#else
case CPUCLASS_K8:
- if (tsc_freq != 0) {
- hw_clockrate = (tsc_freq + 5000) / 1000000;
- printf("%jd.%02d-MHz ",
- (intmax_t)(tsc_freq + 4999) / 1000000,
- (u_int)((tsc_freq + 4999) / 10000) % 100);
- }
printf("K8");
break;
+#endif
default:
printf("Unknown"); /* will panic below... */
}
@@ -207,10 +708,21 @@ printcpuinfo(void)
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
- cpu_vendor_id == CPU_VENDOR_CENTAUR) {
+ cpu_vendor_id == CPU_VENDOR_CENTAUR ||
+#ifdef __i386__
+ cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
+ cpu_vendor_id == CPU_VENDOR_RISE ||
+ cpu_vendor_id == CPU_VENDOR_NSC ||
+ (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
+#endif
+ 0) {
printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
+#ifdef __i386__
+ if (cpu_vendor_id == CPU_VENDOR_CYRIX)
+ printf("\n DIR=0x%04x", cyrix_did);
+#endif
/*
* AMD CPUID Specification
@@ -441,7 +953,18 @@ printcpuinfo(void)
}
}
+#ifdef __i386__
+ } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
+ printf(" DIR=0x%04x", cyrix_did);
+ printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
+ printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
+#ifndef CYRIX_CACHE_REALLY_WORKS
+ if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
+ printf("\n CPU cache: write-through mode");
+#endif
+#endif
}
+
/* Avoid ugly blank lines: only print newline when we have to. */
if (*cpu_vendor || cpu_id)
printf("\n");
@@ -451,30 +974,189 @@ printcpuinfo(void)
if (cpu_vendor_id == CPU_VENDOR_AMD)
print_AMD_info();
+ else if (cpu_vendor_id == CPU_VENDOR_INTEL)
+ print_INTEL_info();
+#ifdef __i386__
+ else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
+ print_transmeta_info();
+#endif
}
void
panicifcpuunsupported(void)
{
+#ifdef __i386__
+#if !defined(lint)
+#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
+#error This kernel is not configured for one of the supported CPUs
+#endif
+#else /* lint */
+#endif /* lint */
+#else /* __amd64__ */
#ifndef HAMMER
#error "You need to specify a cpu type"
#endif
+#endif
/*
* Now that we have told the user what they have,
* let them know if that machine type isn't configured.
*/
switch (cpu_class) {
+#ifdef __i386__
+ case CPUCLASS_286: /* a 286 should not make it this far, anyway */
+ case CPUCLASS_386:
+#if !defined(I486_CPU)
+ case CPUCLASS_486:
+#endif
+#if !defined(I586_CPU)
+ case CPUCLASS_586:
+#endif
+#if !defined(I686_CPU)
+ case CPUCLASS_686:
+#endif
+#else /* __amd64__ */
case CPUCLASS_X86:
#ifndef HAMMER
case CPUCLASS_K8:
#endif
+#endif
panic("CPU class not configured");
default:
break;
}
}
+#ifdef __i386__
+static volatile u_int trap_by_rdmsr;
+
+/*
+ * Special exception 6 handler.
+ * The rdmsr instruction generates invalid opcodes fault on 486-class
+ * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
+ * function identblue() when this handler is called. Stacked eip should
+ * be advanced.
+ */
+inthand_t bluetrap6;
+#ifdef __GNUCLIKE_ASM
+__asm
+(" \n\
+ .text \n\
+ .p2align 2,0x90 \n\
+ .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
+" __XSTRING(CNAME(bluetrap6)) ": \n\
+ ss \n\
+ movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
+ addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
+ iret \n\
+");
+#endif
+
+/*
+ * Special exception 13 handler.
+ * Accessing non-existent MSR generates general protection fault.
+ */
+inthand_t bluetrap13;
+#ifdef __GNUCLIKE_ASM
+__asm
+(" \n\
+ .text \n\
+ .p2align 2,0x90 \n\
+ .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
+" __XSTRING(CNAME(bluetrap13)) ": \n\
+ ss \n\
+ movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
+ popl %eax /* discard error code */ \n\
+ addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
+ iret \n\
+");
+#endif
+
+/*
+ * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
+ * support cpuid instruction. This function should be called after
+ * loading interrupt descriptor table register.
+ *
+ * I don't like this method that handles fault, but I couldn't get
+ * information for any other methods. Does blue giant know?
+ */
+static int
+identblue(void)
+{
+
+ trap_by_rdmsr = 0;
+
+ /*
+ * Cyrix 486-class CPU does not support rdmsr instruction.
+ * The rdmsr instruction generates invalid opcode fault, and exception
+ * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
+ * bluetrap6() set the magic number to trap_by_rdmsr.
+ */
+ setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
+ GSEL(GCODE_SEL, SEL_KPL));
+
+ /*
+ * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
+ * In this case, rdmsr generates general protection fault, and
+ * exception will be trapped by bluetrap13().
+ */
+ setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
+ GSEL(GCODE_SEL, SEL_KPL));
+
+ rdmsr(0x1002); /* Cyrix CPU generates fault. */
+
+ if (trap_by_rdmsr == 0xa8c1d)
+ return IDENTBLUE_CYRIX486;
+ else if (trap_by_rdmsr == 0xa89c4)
+ return IDENTBLUE_CYRIXM2;
+ return IDENTBLUE_IBMCPU;
+}
+
+
+/*
+ * identifycyrix() set lower 16 bits of cyrix_did as follows:
+ *
+ * F E D C B A 9 8 7 6 5 4 3 2 1 0
+ * +-------+-------+---------------+
+ * | SID | RID | Device ID |
+ * | (DIR 1) | (DIR 0) |
+ * +-------+-------+---------------+
+ */
+static void
+identifycyrix(void)
+{
+ register_t saveintr;
+ int ccr2_test = 0, dir_test = 0;
+ u_char ccr2, ccr3;
+
+ saveintr = intr_disable();
+
+ ccr2 = read_cyrix_reg(CCR2);
+ write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
+ read_cyrix_reg(CCR2);
+ if (read_cyrix_reg(CCR2) != ccr2)
+ ccr2_test = 1;
+ write_cyrix_reg(CCR2, ccr2);
+
+ ccr3 = read_cyrix_reg(CCR3);
+ write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
+ read_cyrix_reg(CCR3);
+ if (read_cyrix_reg(CCR3) != ccr3)
+ dir_test = 1; /* CPU supports
DIRs. */
+ write_cyrix_reg(CCR3, ccr3);
+
+ if (dir_test) {
+ /* Device ID registers are available. */
+ cyrix_did = read_cyrix_reg(DIR1) << 8;
+ cyrix_did += read_cyrix_reg(DIR0);
+ } else if (ccr2_test)
+ cyrix_did = 0x0010; /* 486S A-step */
+ else
+ cyrix_did = 0x00ff; /* Old 486SLC/DLC and
TI486SXLC/SXL */
+
+ intr_restore(saveintr);
+}
+#endif
/* Update TSC freq with the value indicated by the caller. */
static void
@@ -505,24 +1187,35 @@ SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE,
/*
* Final stage of CPU identification.
*/
+#ifdef __i386__
+void
+finishidentcpu(void)
+#else
void
identify_cpu(void)
+#endif
{
u_int regs[4], cpu_stdext_disable;
+#ifdef __i386__
+ u_char ccr3;
+#endif
+#ifdef __amd64__
do_cpuid(0, regs);
cpu_high = regs[0];
((u_int *)&cpu_vendor)[0] = regs[1];
((u_int *)&cpu_vendor)[1] = regs[3];
((u_int *)&cpu_vendor)[2] = regs[2];
cpu_vendor[12] = '\0';
- cpu_vendor_id = find_cpu_vendor_id();
do_cpuid(1, regs);
cpu_id = regs[0];
cpu_procinfo = regs[1];
cpu_feature = regs[3];
cpu_feature2 = regs[2];
+#endif
+
+ cpu_vendor_id = find_cpu_vendor_id();
/*
* Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
@@ -530,7 +1223,9 @@ identify_cpu(void)
* for probing correct CPU topology later.
* XXX This is only done on the BSP package.
*/
- if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) {
+ if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
+ ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3)
||
+ (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe)))
{
uint64_t msr;
msr = rdmsr(MSR_IA32_MISC_ENABLE);
if ((msr & 0x400000ULL) != 0) {
@@ -566,12 +1261,25 @@ identify_cpu(void)
cpu_stdext_feature &= ~cpu_stdext_disable;
}
+#ifdef __i386__
+ if (cpu_high > 0 &&
+ (cpu_vendor_id == CPU_VENDOR_INTEL ||
+ cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
+ cpu_vendor_id == CPU_VENDOR_CENTAUR ||
+ cpu_vendor_id == CPU_VENDOR_NSC)) {
+ do_cpuid(0x80000000, regs);
+ if (regs[0] >= 0x80000000)
+ cpu_exthigh = regs[0];
+ }
+#else
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_CENTAUR) {
do_cpuid(0x80000000, regs);
cpu_exthigh = regs[0];
}
+#endif
if (cpu_exthigh >= 0x80000001) {
do_cpuid(0x80000001, regs);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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