Author: br
Date: Thu Sep 4 12:44:40 2014
New Revision: 271093
URL: http://svnweb.freebsd.org/changeset/base/271093
Log:
Add initial support for Altera SOCFPGA (heterogeneous ARM/FPGA) SoC family.
Include board configuration for Terasic SoCKit (Altera Cyclone V).
Sponsored by: DARPA, AFRL
Added:
head/sys/arm/altera/
head/sys/arm/altera/socfpga/
head/sys/arm/altera/socfpga/files.socfpga (contents, props changed)
head/sys/arm/altera/socfpga/socfpga_common.c (contents, props changed)
head/sys/arm/altera/socfpga/socfpga_machdep.c (contents, props changed)
head/sys/arm/altera/socfpga/std.socfpga (contents, props changed)
head/sys/arm/conf/SOCKIT (contents, props changed)
head/sys/boot/fdt/dts/arm/socfpga-sockit.dts (contents, props changed)
head/sys/boot/fdt/dts/arm/socfpga.dtsi (contents, props changed)
Added: head/sys/arm/altera/socfpga/files.socfpga
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/altera/socfpga/files.socfpga Thu Sep 4 12:44:40 2014
(r271093)
@@ -0,0 +1,17 @@
+# $FreeBSD$
+
+kern/kern_clocksource.c standard
+
+arm/arm/bus_space_generic.c standard
+arm/arm/bus_space_asm_generic.S standard
+arm/arm/cpufunc_asm_armv5.S standard
+arm/arm/cpufunc_asm_arm10.S standard
+arm/arm/cpufunc_asm_arm11.S standard
+arm/arm/cpufunc_asm_armv7.S standard
+
+arm/arm/bus_space-v6.c standard
+arm/arm/gic.c standard
+arm/arm/mpcore_timer.c standard
+
+arm/altera/socfpga/socfpga_common.c standard
+arm/altera/socfpga/socfpga_machdep.c standard
Added: head/sys/arm/altera/socfpga/socfpga_common.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/altera/socfpga/socfpga_common.c Thu Sep 4 12:44:40
2014 (r271093)
@@ -0,0 +1,83 @@
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <b...@bsdpad.com>
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#define RESMAN_BASE 0xFFD05000
+#define RESMAN_CTRL 0x4
+#define SWWARMRSTREQ (1 << 1)
+
+void
+cpu_reset(void)
+{
+ bus_addr_t vaddr;
+
+ if (bus_space_map(fdtbus_bs_tag, RESMAN_BASE, 0x10, 0, &vaddr) == 0) {
+ bus_space_write_4(fdtbus_bs_tag, vaddr,
+ RESMAN_CTRL, SWWARMRSTREQ);
+ }
+
+ while (1);
+}
+
+struct fdt_fixup_entry fdt_fixup_table[] = {
+ { NULL, NULL }
+};
+
+static int
+fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
+ int *pol)
+{
+
+ if (!fdt_is_compatible(node, "arm,gic"))
+ return (ENXIO);
+
+ *interrupt = fdt32_to_cpu(intr[0]);
+ *trig = INTR_TRIGGER_CONFORM;
+ *pol = INTR_POLARITY_CONFORM;
+ return (0);
+}
+
+fdt_pic_decode_t fdt_pic_table[] = {
+ &fdt_pic_decode_ic,
+ NULL
+};
Added: head/sys/arm/altera/socfpga/socfpga_machdep.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/altera/socfpga/socfpga_machdep.c Thu Sep 4 12:44:40
2014 (r271093)
@@ -0,0 +1,107 @@
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <b...@bsdpad.com>
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_ddb.h"
+#include "opt_platform.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <vm/vm.h>
+
+#include <machine/armreg.h>
+#include <machine/bus.h>
+#include <machine/devmap.h>
+#include <machine/machdep.h>
+#include <machine/platform.h>
+
+vm_offset_t
+platform_lastaddr(void)
+{
+
+ return (arm_devmap_lastaddr());
+}
+
+void
+platform_probe_and_attach(void)
+{
+
+}
+
+void
+platform_gpio_init(void)
+{
+
+}
+
+void
+platform_late_init(void)
+{
+
+}
+
+int
+platform_devmap_init(void)
+{
+
+ /* UART */
+ arm_devmap_add_entry(0xffc00000, 0x100000);
+
+ /*
+ * USB OTG
+ *
+ * We use static device map for USB due to some bug in the Altera
+ * which throws Translation Fault (P) exception on high load.
+ * It might be caused due to some power save options being turned
+ * on or something else.
+ */
+ arm_devmap_add_entry(0xffb00000, 0x100000);
+
+ return (0);
+}
+
+struct arm32_dma_range *
+bus_dma_get_range(void)
+{
+
+ return (NULL);
+}
+
+int
+bus_dma_get_range_nb(void)
+{
+
+ return (0);
+}
Added: head/sys/arm/altera/socfpga/std.socfpga
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/altera/socfpga/std.socfpga Thu Sep 4 12:44:40 2014
(r271093)
@@ -0,0 +1,21 @@
+# $FreeBSD$
+
+makeoption ARM_LITTLE_ENDIAN
+
+cpu CPU_CORTEXA
+machine arm armv6
+
+options PHYSADDR=0x00000000
+
+makeoptions KERNPHYSADDR=0x00f00000
+options KERNPHYSADDR=0x00f00000
+
+makeoptions KERNVIRTADDR=0xc0f00000
+options KERNVIRTADDR=0xc0f00000
+
+options ARM_L2_PIPT
+
+options IPI_IRQ_START=0
+options IPI_IRQ_END=15
+
+files "../altera/socfpga/files.socfpga"
Added: head/sys/arm/conf/SOCKIT
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/SOCKIT Thu Sep 4 12:44:40 2014 (r271093)
@@ -0,0 +1,136 @@
+# Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC).
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#
http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+ident SOCKIT
+include "../altera/socfpga/std.socfpga"
+
+makeoptions MODULES_OVERRIDE=""
+
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+makeoptions WERROR="-Werror"
+
+options HZ=100
+options SCHED_4BSD # 4BSD scheduler
+options INET # InterNETworking
+options INET6 # IPv6 communications protocols
+options GEOM_PART_BSD # BSD partition scheme
+options GEOM_PART_MBR # MBR partition scheme
+options GEOM_PART_GPT # GUID partition tables
+options TMPFS # Efficient memory filesystem
+options FFS # Berkeley Fast Filesystem
+options SOFTUPDATES
+options UFS_ACL # Support for access control lists
+options UFS_DIRHASH # Improve performance on big directories
+options MSDOSFS # MSDOS Filesystem
+options CD9660 # ISO 9660 Filesystem
+options PROCFS # Process filesystem (requires PSEUDOFS)
+options PSEUDOFS # Pseudo-filesystem framework
+options COMPAT_43 # Compatible with BSD 4.3 [KEEP THIS!]
+options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI
+options KTRACE
+options SYSVSHM # SYSV-style shared memory
+options SYSVMSG # SYSV-style message queues
+options SYSVSEM # SYSV-style semaphores
+options _KPOSIX_PRIORITY_SCHEDULING # Posix P1003_1B real-time
extensions
+options KBD_INSTALL_CDEV
+options PREEMPTION
+options FREEBSD_BOOT_LOADER
+options VFP # vfp/neon
+
+#options SMP
+
+# Debugging
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+options BREAK_TO_DEBUGGER
+#options VERBOSE_SYSINIT # Enable verbose sysinit messages
+options KDB
+options DDB # Enable the kernel debugger
+options INVARIANTS # Enable calls of extra sanity checking
+options INVARIANT_SUPPORT # Extra sanity checks of internal
structures, required by INVARIANTS
+#options WITNESS # Enable checks to detect deadlocks and
cycles
+#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for
speed
+#options DIAGNOSTIC
+
+# NFS support
+options NFSCL # Network Filesystem Client
+options NFSLOCKD # Network Lock Manager
+options NFS_ROOT # NFS usable as /, requires NFSCLIENT
+
+# Uncomment this for NFS root
+#options NFS_ROOT # NFS usable as /, requires NFSCL
+#options BOOTP_NFSROOT
+#options BOOTP_COMPAT
+#options BOOTP
+#options BOOTP_NFSV3
+#options BOOTP_WIRED_TO=ue0
+
+device mmc # mmc/sd bus
+device mmcsd # mmc/sd flash cards
+device sdhci # generic sdhci
+
+options ROOTDEVNAME=\"ufs:/dev/da0\"
+
+# Pseudo devices
+
+device loop
+device random
+device pty
+device md
+device gpio
+
+# USB support
+options USB_HOST_ALIGN=64 # Align usb buffers to cache line size.
+device usb
+options USB_DEBUG
+#options USB_REQ_DEBUG
+#options USB_VERBOSE
+#device musb
+device dwcotg
+
+device umass
+device scbus # SCSI bus (required for ATA/SCSI)
+device da # Direct Access (disks)
+device pass
+
+# Serial ports
+device uart
+device uart_ns8250
+
+# I2C (TWSI)
+device iic
+device iicbus
+
+# SPI
+device spibus
+
+# Ethernet
+device ether
+device mii
+device smsc
+device smscphy
+
+# USB ethernet support, requires miibus
+device miibus
+device axe # ASIX Electronics USB Ethernet
+device bpf # Berkeley packet filter
+
+#FDT
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=socfpga-sockit.dts
Added: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/socfpga-sockit.dts Thu Sep 4 12:44:40
2014 (r271093)
@@ -0,0 +1,61 @@
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <b...@bsdpad.com>
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/include/ "socfpga.dtsi"
+
+/ {
+ model = "Terasic SoCKit";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ memory {
+ device_type = "memory";
+ reg = < 0x00000000 0x40000000 >; /* 1G RAM */
+ };
+
+ SOC: socfpga {
+ serial0: serial@ffc02000 {
+ status = "okay";
+ };
+
+ usb1: usb@ffb40000 {
+ status = "okay";
+ };
+ };
+
+ chosen {
+ bootargs = "-v";
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Added: head/sys/boot/fdt/dts/arm/socfpga.dtsi
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/socfpga.dtsi Thu Sep 4 12:44:40 2014
(r271093)
@@ -0,0 +1,111 @@
+/*-
+ * Copyright (c) 2014 Ruslan Bukin <b...@bsdpad.com>
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/ {
+ compatible = "altr,socfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&GIC>;
+
+ aliases {
+ soc = &SOC;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ SOC: socfpga {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bus-frequency = <0>;
+
+ GIC: interrupt-controller@fffed000 {
+ compatible = "arm,gic";
+ reg = < 0xfffed000 0x1000 >, /* Distributor */
+ < 0xfffec100 0x100 >; /* CPU Interface */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ mp_tmr@40002100 {
+ compatible = "arm,mpcore-timers";
+ clock-frequency = <200000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0xfffec200 0x100 >, /* Global Timer */
+ < 0xfffec600 0x100 >; /* Private Timer */
+ interrupts = < 27 29 >;
+ interrupt-parent = < &GIC >;
+ };
+
+ serial0: serial@ffc02000 {
+ compatible = "ns16550";
+ reg = <0xffc02000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <194>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 100000000 >;
+ status = "disabled";
+ };
+
+ serial1: serial@ffc03000 {
+ compatible = "ns16550";
+ reg = <0xffc03000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <195>;
+ interrupt-parent = <&GIC>;
+ current-speed = <115200>;
+ clock-frequency = < 100000000 >;
+ status = "disabled";
+ };
+
+ usb0: usb@ffb00000 {
+ compatible = "synopsys,designware-hs-otg2";
+ reg = <0xffb00000 0xffff>;
+ interrupts = <157>;
+ interrupt-parent = <&GIC>;
+ status = "disabled";
+ };
+
+ usb1: usb@ffb40000 {
+ compatible = "synopsys,designware-hs-otg2";
+ reg = <0xffb40000 0xffff>;
+ interrupts = <160>;
+ interrupt-parent = <&GIC>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+ };
+};
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