Author: bz
Date: Thu Jun 26 17:10:07 2014
New Revision: 267920
URL: http://svnweb.freebsd.org/changeset/base/267920
Log:
Allow switching between 32bit and 64bit bus width data access at compile
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.
Adjust comments to indicate the 32 or 64bit register widths.
MFC after: 2 weeks
Modified:
head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c
head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c
Modified: head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c
==============================================================================
--- head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c Thu Jun 26 17:03:08
2014 (r267919)
+++ head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac.c Thu Jun 26 17:10:07
2014 (r267920)
@@ -117,40 +117,62 @@ static poll_handler_t nf10bmac_poll;
#define NF10BMAC_DATA_SPORT_MASK 0x00ff0000
#define NF10BMAC_DATA_SPORT_SHIFT 16
#define NF10BMAC_DATA_LAST 0x00008000
+#ifdef NF10BMAC_64BIT
+#define NF10BMAC_DATA_STRB 0x000000ff
+#define REGWTYPE uint64_t
+#else
#define NF10BMAC_DATA_STRB 0x0000000f
+#define REGWTYPE uint32_t
+#endif
static inline void
-nf10bmac_write(struct resource *res, uint32_t reg, uint32_t val,
+nf10bmac_write(struct resource *res, REGWTYPE reg, REGWTYPE val,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ bus_write_8(res, reg, htole64(val));
+#else
bus_write_4(res, reg, htole32(val));
+#endif
}
-static inline uint32_t
-nf10bmac_read(struct resource *res, uint32_t reg,
+static inline REGWTYPE
+nf10bmac_read(struct resource *res, REGWTYPE reg,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ return (le64toh(bus_read_8(res, reg)));
+#else
return (le32toh(bus_read_4(res, reg)));
+#endif
}
static inline void
-nf10bmac_write_be(struct resource *res, uint32_t reg, uint32_t val,
+nf10bmac_write_be(struct resource *res, REGWTYPE reg, REGWTYPE val,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ bus_write_8(res, reg, htobe64(val));
+#else
bus_write_4(res, reg, htobe32(val));
+#endif
}
-static inline uint32_t
-nf10bmac_read_be(struct resource *res, uint32_t reg,
+static inline REGWTYPE
+nf10bmac_read_be(struct resource *res, REGWTYPE reg,
const char *f __unused, const int l __unused)
{
+#ifdef NF10BMAC_64BIT
+ return (be64toh(bus_read_8(res, reg)));
+#else
return (be32toh(bus_read_4(res, reg)));
+#endif
}
#define NF10BMAC_WRITE_CTRL(sc, reg, val)
\
@@ -196,7 +218,7 @@ static int
nf10bmac_tx_locked(struct nf10bmac_softc *sc, struct mbuf *m)
{
int32_t len, l, ml;
- uint32_t md, val;
+ REGWTYPE md, val;
NF10BMAC_LOCK_ASSERT(sc);
@@ -311,7 +333,7 @@ nf10bmac_start(struct ifnet *ifp)
static void
nf10bmac_eat_packet_munch_munch(struct nf10bmac_softc *sc)
{
- uint32_t md, val;
+ REGWTYPE md, val;
do {
md = NF10BMAC_READ_BE(sc, NF10BMAC_RX_META);
@@ -326,7 +348,7 @@ nf10bmac_rx_locked(struct nf10bmac_softc
{
struct ifnet *ifp;
struct mbuf *m;
- uint32_t md, val;
+ REGWTYPE md, val;
int32_t len, l;
/*
@@ -421,7 +443,7 @@ nf10bmac_rx_locked(struct nf10bmac_softc
/* We should get out of this loop with tlast and tsrb. */
if ((md & NF10BMAC_DATA_LAST) == 0 || (md & NF10BMAC_DATA_STRB) == 0) {
device_printf(sc->nf10bmac_dev, "Unexpected rx loop end state: "
- "md=0x%08x len=%d l=%d\n", md, len, l);
+ "md=0x%08jx len=%d l=%d\n", (uintmax_t)md, len, l);
ifp->if_ierrors++;
m_freem(m);
return (0);
Modified: head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c
==============================================================================
--- head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c Thu Jun 26 17:03:08
2014 (r267919)
+++ head/sys/dev/netfpga10g/nf10bmac/if_nf10bmac_fdt.c Thu Jun 26 17:10:07
2014 (r267920)
@@ -90,7 +90,7 @@ nf10bmac_attach_fdt(device_t dev)
/*
* LOOP memory region (this could be a general control region).
- * 0x00: 32bit register to enable a Y-"lopback".
+ * 0x00: 32/64bit register to enable a Y-"lopback".
*/
sc->nf10bmac_ctrl_rid = 0;
sc->nf10bmac_ctrl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
@@ -108,9 +108,9 @@ nf10bmac_attach_fdt(device_t dev)
/*
* TX and TX metadata FIFO memory region.
- * 0x00: 32bit FIFO data,
- * 0x08: 32bit FIFO metadata,
- * 0x10: 32bit packet length.
+ * 0x00: 32/64bit FIFO data,
+ * 0x08: 32/64bit FIFO metadata,
+ * 0x10: 32/64bit packet length.
*/
sc->nf10bmac_tx_mem_rid = 1;
sc->nf10bmac_tx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
@@ -128,9 +128,9 @@ nf10bmac_attach_fdt(device_t dev)
/*
* RX and RXC metadata FIFO memory region.
- * 0x00: 32bit FIFO data,
- * 0x08: 32bit FIFO metadata,
- * 0x10: 32bit packet length.
+ * 0x00: 32/64bit FIFO data,
+ * 0x08: 32/64bit FIFO metadata,
+ * 0x10: 32/64bit packet length.
*/
sc->nf10bmac_rx_mem_rid = 2;
sc->nf10bmac_rx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
@@ -148,8 +148,8 @@ nf10bmac_attach_fdt(device_t dev)
/*
* Interrupt handling registers.
- * 0x00: 32bit register to clear (and disable) the RX interrupt.
- * 0x08: 32bit register to enable or disable the RX interrupt.
+ * 0x00: 32/64bit register to clear (and disable) the RX interrupt.
+ * 0x08: 32/64bit register to enable or disable the RX interrupt.
*/
sc->nf10bmac_intr_rid = 3;
sc->nf10bmac_intr_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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