Author: ian
Date: Thu Feb 27 22:55:33 2014
New Revision: 262581
URL: http://svnweb.freebsd.org/changeset/base/262581
Log:
Initialize the Low Power Mode bits to keep the ARM cores running during WFI.
Modified:
head/sys/arm/freescale/imx/imx6_ccm.c
head/sys/arm/freescale/imx/imx6_ccmreg.h
Modified: head/sys/arm/freescale/imx/imx6_ccm.c
==============================================================================
--- head/sys/arm/freescale/imx/imx6_ccm.c Thu Feb 27 22:44:07 2014
(r262580)
+++ head/sys/arm/freescale/imx/imx6_ccm.c Thu Feb 27 22:55:33 2014
(r262581)
@@ -92,6 +92,7 @@ ccm_attach(device_t dev)
{
struct ccm_softc *sc;
int err, rid;
+ uint32_t reg;
sc = device_get_softc(dev);
err = 0;
@@ -107,6 +108,26 @@ ccm_attach(device_t dev)
}
ccm_sc = sc;
+
+ /*
+ * Configure the Low Power Mode setting to leave the ARM core power on
+ * when a WFI instruction is executed. This lets the MPCore timers and
+ * GIC continue to run, which is helpful when the only thing that can
+ * wake you up is an MPCore Private Timer interrupt delivered via GIC.
+ *
+ * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be
+ * required when the LPM bits are set to LPM_RUN. But experimentally
+ * I've experienced a fairly rare lockup when not setting it. I was
+ * unable to prove conclusively that the lockup was related to power
+ * management or that this definitively fixes it. Revisit this.
+ */
+ reg = RD4(sc, CCM_CGPR);
+ reg |= CCM_CGPR_INT_MEM_CLK_LPM;
+ WR4(sc, CCM_CGPR, reg);
+ reg = RD4(sc, CCM_CLPCR);
+ reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
+ WR4(sc, CCM_CLPCR, reg);
+
err = 0;
out:
Modified: head/sys/arm/freescale/imx/imx6_ccmreg.h
==============================================================================
--- head/sys/arm/freescale/imx/imx6_ccmreg.h Thu Feb 27 22:44:07 2014
(r262580)
+++ head/sys/arm/freescale/imx/imx6_ccmreg.h Thu Feb 27 22:55:33 2014
(r262581)
@@ -29,13 +29,20 @@
#ifndef IMX6_CCMREG_H
#define IMX6_CCMREG_H
-#define CCM_CCGR1 0x06C
-#define CCM_CCGR2 0x070
-#define CCM_CCGR3 0x074
-#define CCM_CCGR4 0x078
-#define CCM_CCGR5 0x07C
-#define CCM_CCGR6 0x080
-#define CCM_CMEOR 0x088
+#define CCM_CLPCR 0x054
+#define CCM_CLPCR_LPM_MASK 0x03
+#define CCM_CLPCR_LPM_RUN 0x00
+#define CCM_CLPCR_LPM_WAIT 0x01
+#define CCM_CLPCR_LPM_STOP 0x02
+#define CCM_CGPR 0x064
+#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17)
+#define CCM_CCGR1 0x06C
+#define CCM_CCGR2 0x070
+#define CCM_CCGR3 0x074
+#define CCM_CCGR4 0x078
+#define CCM_CCGR5 0x07C
+#define CCM_CCGR6 0x080
+#define CCM_CMEOR 0x088
#endif
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