Author: ian
Date: Sun Feb 23 22:52:48 2014
New Revision: 262411
URL: http://svnweb.freebsd.org/changeset/base/262411
Log:
If the L2 cache type is PIPT, pass a physical address for a flush.
While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.
Modified:
head/sys/arm/arm/machdep.c
Modified: head/sys/arm/arm/machdep.c
==============================================================================
--- head/sys/arm/arm/machdep.c Sun Feb 23 22:50:22 2014 (r262410)
+++ head/sys/arm/arm/machdep.c Sun Feb 23 22:52:48 2014 (r262411)
@@ -410,7 +410,11 @@ cpu_flush_dcache(void *ptr, size_t len)
{
cpu_dcache_wb_range((uintptr_t)ptr, len);
+#ifdef ARM_L2_PIPT
+ cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
+#else
cpu_l2cache_wb_range((uintptr_t)ptr, len);
+#endif
}
/* Get current clock frequency for the given cpu id. */
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