Author: neel
Date: Mon Feb 17 23:07:16 2014
New Revision: 262140
URL: http://svnweb.freebsd.org/changeset/base/262140
Log:
Handle writes to the SELF_IPI MSR by the guest when the vlapic is configured
in x2apic mode. Reads to this MSR are currently ignored but should cause a
general proctection exception to be injected into the vcpu.
All accesses to the corresponding offset in xAPIC mode are ignored.
Also, do not panic the host if there is mismatch between the trigger mode
programmed in the TMR and the actual interrupt being delivered. Instead the
anomaly is logged to aid debugging and to prevent a misbehaving guest from
panicking the host.
Modified:
head/sys/amd64/vmm/io/vlapic.c
head/sys/amd64/vmm/io/vlapic_priv.h
Modified: head/sys/amd64/vmm/io/vlapic.c
==============================================================================
--- head/sys/amd64/vmm/io/vlapic.c Mon Feb 17 22:57:51 2014
(r262139)
+++ head/sys/amd64/vmm/io/vlapic.c Mon Feb 17 23:07:16 2014
(r262140)
@@ -289,9 +289,11 @@ vlapic_set_intr_ready(struct vlapic *vla
* the vlapic TMR registers.
*/
tmrptr = &lapic->tmr0;
- KASSERT((tmrptr[idx] & mask) == (level ? mask : 0),
- ("vlapic TMR[%d] is 0x%08x but interrupt is %s-triggered",
- idx / 4, tmrptr[idx], level ? "level" : "edge"));
+ if ((tmrptr[idx] & mask) != (level ? mask : 0)) {
+ VLAPIC_CTR3(vlapic, "vlapic TMR[%d] is 0x%08x but "
+ "interrupt is %s-triggered", idx / 4, tmrptr[idx],
+ level ? "level" : "edge");
+ }
VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready");
return (1);
@@ -997,6 +999,18 @@ vlapic_icrlo_write_handler(struct vlapic
return (1);
}
+static void
+vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val)
+{
+ int vec;
+
+ vec = val & 0xff;
+ lapic_intr_edge(vlapic->vm, vlapic->vcpuid, vec);
+ vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid, IPIS_SENT,
+ vlapic->vcpuid, 1);
+ VLAPIC_CTR1(vlapic, "vlapic self-ipi %d", vec);
+}
+
int
vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
{
@@ -1190,6 +1204,12 @@ vlapic_read(struct vlapic *vlapic, uint6
case APIC_OFFSET_TIMER_DCR:
*data = lapic->dcr_timer;
break;
+ case APIC_OFFSET_SELF_IPI:
+ /*
+ * XXX generate a GP fault if vlapic is in x2apic mode
+ */
+ *data = 0;
+ break;
case APIC_OFFSET_RRR:
default:
*data = 0;
@@ -1270,6 +1290,12 @@ vlapic_write(struct vlapic *vlapic, uint
case APIC_OFFSET_ESR:
vlapic_esr_write_handler(vlapic);
break;
+
+ case APIC_OFFSET_SELF_IPI:
+ if (x2apic(vlapic))
+ vlapic_self_ipi_handler(vlapic, data);
+ break;
+
case APIC_OFFSET_VER:
case APIC_OFFSET_APR:
case APIC_OFFSET_PPR:
Modified: head/sys/amd64/vmm/io/vlapic_priv.h
==============================================================================
--- head/sys/amd64/vmm/io/vlapic_priv.h Mon Feb 17 22:57:51 2014
(r262139)
+++ head/sys/amd64/vmm/io/vlapic_priv.h Mon Feb 17 23:07:16 2014
(r262140)
@@ -81,6 +81,7 @@
#define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */
#define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */
#define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */
+#define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */
#define VLAPIC_CTR0(vlapic, format)
\
VCPU_CTR0((vlapic)->vm, (vlapic)->vcpuid, format)
@@ -91,6 +92,9 @@
#define VLAPIC_CTR2(vlapic, format, p1, p2)
\
VCPU_CTR2((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2)
+#define VLAPIC_CTR3(vlapic, format, p1, p2, p3)
\
+ VCPU_CTR3((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2, p3)
+
#define VLAPIC_CTR_IRR(vlapic, msg)
\
do { \
uint32_t *irrptr = &(vlapic)->apic_page->irr0; \
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