Author: ian
Date: Sun Jan 5 18:40:06 2014
New Revision: 260326
URL: http://svnweb.freebsd.org/changeset/base/260326
Log:
Convert from using fdt_immr style to arm_devmap_add_entry() to make
static device mappings.
This SoC relied heavily on the fact that all devices were static-mapped
at a fixed address, and it (rather bogusly) used bus_space read and write
calls passing hard-coded virtual addresses instead of proper bus handles,
relying on the fact that the virtual addresses of the mappings were known
at compile time, and relying on the implementation details of arm
bus_space never changing. All such usage was replaced with calls to
bus_space_map() to obtain a proper bus handle for the read/write calls.
This required adjusting some of the #define values that map out hardware
registers, and some of them were renamed in the process to make it clear
which were defining absolute physical addresses and which were defining
offsets. (The ones that just define offsets don't appear to be referenced
and probably serve no value other than perhaps documentation.)
Modified:
head/sys/arm/lpc/lpc_gpio.c
head/sys/arm/lpc/lpc_machdep.c
head/sys/arm/lpc/lpc_mmc.c
head/sys/arm/lpc/lpcreg.h
head/sys/dev/uart/uart_dev_lpc.c
Modified: head/sys/arm/lpc/lpc_gpio.c
==============================================================================
--- head/sys/arm/lpc/lpc_gpio.c Sun Jan 5 17:33:10 2014 (r260325)
+++ head/sys/arm/lpc/lpc_gpio.c Sun Jan 5 18:40:06 2014 (r260326)
@@ -502,12 +502,18 @@ lpc_gpio_get_state(device_t dev, int pin
void
platform_gpio_init()
{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ bst = fdtbus_bs_tag;
+
/* Preset SPI devices CS pins to one */
- bus_space_write_4(fdtbus_bs_tag,
- LPC_GPIO_BASE, LPC_GPIO_P3_OUTP_SET,
+ bus_space_map(bst, LPC_GPIO_PHYS_BASE, LPC_GPIO_SIZE, 0, &bsh);
+ bus_space_write_4(bst, bsh, LPC_GPIO_P3_OUTP_SET,
1 << (SSD1289_CS_PIN - LPC_GPIO_GPO_00(0)) |
1 << (SSD1289_DC_PIN - LPC_GPIO_GPO_00(0)) |
1 << (ADS7846_CS_PIN - LPC_GPIO_GPO_00(0)));
+ bus_space_unmap(bst, bsh, LPC_GPIO_SIZE);
}
static device_method_t lpc_gpio_methods[] = {
Modified: head/sys/arm/lpc/lpc_machdep.c
==============================================================================
--- head/sys/arm/lpc/lpc_machdep.c Sun Jan 5 17:33:10 2014
(r260325)
+++ head/sys/arm/lpc/lpc_machdep.c Sun Jan 5 18:40:06 2014
(r260326)
@@ -57,21 +57,17 @@ __FBSDID("$FreeBSD$");
#include <arm/lpc/lpcvar.h>
#include <dev/fdt/fdt_common.h>
-#include <dev/ic/ns16550.h>
vm_offset_t
initarm_lastaddr(void)
{
- return (fdt_immr_va);
+ return (arm_devmap_lastaddr());
}
void
initarm_early_init(void)
{
-
- if (fdt_immr_addr(LPC_DEV_BASE) != 0)
- while (1);
}
void
@@ -89,28 +85,16 @@ initarm_late_init(void)
{
}
-#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1)
-static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
- { 0, 0, 0, 0, 0, }
-};
-
/*
- * Construct pmap_devmap[] with DT-derived config data.
+ * Add a single static device mapping.
+ * The values used were taken from the ranges property of the SoC node in the
+ * dts file when this code was converted to arm_devmap_add_entry().
*/
int
initarm_devmap_init(void)
{
- /*
- * IMMR range.
- */
- fdt_devmap[0].pd_va = fdt_immr_va;
- fdt_devmap[0].pd_pa = fdt_immr_pa;
- fdt_devmap[0].pd_size = fdt_immr_size;
- fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
- fdt_devmap[0].pd_cache = PTE_NOCACHE;
-
- arm_devmap_register_table(&fdt_devmap[0]);
+ arm_devmap_add_entry(LPC_DEV_PHYS_BASE, LPC_DEV_SIZE);
return (0);
}
@@ -131,15 +115,24 @@ bus_dma_get_range_nb(void)
void
cpu_reset(void)
{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ bst = fdtbus_bs_tag;
+
/* Enable WDT */
- bus_space_write_4(fdtbus_bs_tag,
- LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL,
+ bus_space_map(bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh);
+ bus_space_write_4(bst, bsh, LPC_CLKPWR_TIMCLK_CTRL,
LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
+ bus_space_unmap(bst, bsh, LPC_CLKPWR_SIZE);
/* Instant assert of RESETOUT_N with pulse length 1ms */
- bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE,
13000);
- bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70);
+ bus_space_map(bst, LPC_WDTIM_PHYS_BASE, LPC_WDTIM_SIZE, 0, &bsh);
+ bus_space_write_4(bst, bsh, LPC_WDTIM_PULSE, 13000);
+ bus_space_write_4(bst, bsh, LPC_WDTIM_MCTRL, 0x70);
+ bus_space_unmap(bst, bsh, LPC_WDTIM_SIZE);
- for (;;);
+ for (;;)
+ continue;
}
Modified: head/sys/arm/lpc/lpc_mmc.c
==============================================================================
--- head/sys/arm/lpc/lpc_mmc.c Sun Jan 5 17:33:10 2014 (r260325)
+++ head/sys/arm/lpc/lpc_mmc.c Sun Jan 5 18:40:06 2014 (r260326)
@@ -507,14 +507,14 @@ lpc_mmc_setup_xfer(struct lpc_mmc_softc
if (data->flags & MMC_DATA_READ) {
sc->lm_xfer_direction = DIRECTION_READ;
lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
- LPC_SD_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
+ LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
data_words, 0);
}
if (data->flags & MMC_DATA_WRITE) {
sc->lm_xfer_direction = DIRECTION_WRITE;
lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
- sc->lm_buffer_phys, LPC_SD_BASE + LPC_SD_FIFO,
+ sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
data_words, 0);
}
Modified: head/sys/arm/lpc/lpcreg.h
==============================================================================
--- head/sys/arm/lpc/lpcreg.h Sun Jan 5 17:33:10 2014 (r260325)
+++ head/sys/arm/lpc/lpcreg.h Sun Jan 5 18:40:06 2014 (r260326)
@@ -32,7 +32,6 @@
#define LPC_DEV_PHYS_BASE 0x40000000
#define LPC_DEV_P5_PHYS_BASE 0x20000000
#define LPC_DEV_P6_PHYS_BASE 0x30000000
-#define LPC_DEV_BASE 0xd0000000
#define LPC_DEV_SIZE 0x10000000
/*
@@ -88,7 +87,7 @@
/*
* Watchdog timer. (from UM10326: LPC32x0 User manual, page 572)
*/
-#define LPC_WDTIM_BASE (LPC_DEV_BASE + 0x3c000)
+#define LPC_WDTIM_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x3c000)
#define LPC_WDTIM_INT 0x00
#define LPC_WDTIM_CTRL 0x04
#define LPC_WDTIM_COUNTER 0x08
@@ -97,11 +96,12 @@
#define LPC_WDTIM_EMR 0x14
#define LPC_WDTIM_PULSE 0x18
#define LPC_WDTIM_RES 0x1c
+#define LPC_WDTIM_SIZE 0x20
/*
* Clocking and power control. (from UM10326: LPC32x0 User manual, page 58)
*/
-#define LPC_CLKPWR_BASE (LPC_DEV_BASE + 0x4000)
+#define LPC_CLKPWR_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x4000)
#define LPC_CLKPWR_PWR_CTRL 0x44
#define LPC_CLKPWR_OSC_CTRL 0x4c
#define LPC_CLKPWR_SYSCLK_CTRL 0x50
@@ -189,6 +189,7 @@
#define LPC_CLKPWR_UARTCLK_CTRL 0xe4
#define LPC_CLKPWR_POS0_IRAM_CTRL 0x110
#define LPC_CLKPWR_POS1_IRAM_CTRL 0x114
+#define LPC_CLKPWR_SIZE 0x118
/* Additional UART registers in CLKPWR address space. */
#define LPC_CLKPWR_UART_U3CLK 0xd0
@@ -201,9 +202,9 @@
#define LPC_CLKPWR_UART_IRDACLK 0xe0
/* Additional UART registers */
-#define LPC_UART_BASE (LPC_DEV_BASE + 0x80000)
-#define LPC_UART_CONTROL_BASE (LPC_DEV_BASE + 0x54000)
-#define LPC_UART5_BASE (LPC_DEV_BASE + 0x90000)
+#define LPC_UART_BASE 0x80000
+#define LPC_UART_CONTROL_BASE 0x54000
+#define LPC_UART5_BASE 0x90000
#define LPC_UART_CTRL 0x00
#define LPC_UART_CLKMODE 0x04
#define LPC_UART_CLKMODE_UART3(_n) (((_n) & 0x3) << 4)
@@ -211,6 +212,7 @@
#define LPC_UART_CLKMODE_UART5(_n) (((_n) & 0x3) << 8)
#define LPC_UART_CLKMODE_UART6(_n) (((_n) & 0x3) << 10)
#define LPC_UART_LOOP 0x08
+#define LPC_UART_CONTROL_SIZE 0x0c
#define LPC_UART_FIFOSIZE 64
/*
@@ -236,7 +238,7 @@
/*
* MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436)
*/
-#define LPC_SD_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000)
+#define LPC_SD_PHYS_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000)
#define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz
#define LPC_SD_POWER 0x00
#define LPC_SD_POWER_OPENDRAIN (1 << 6)
@@ -535,7 +537,7 @@
/*
* GPIO (from UM10326: LPC32x0 User manual, page 606)
*/
-#define LPC_GPIO_BASE (LPC_DEV_BASE + 0x28000)
+#define LPC_GPIO_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x28000)
#define LPC_GPIO_P0_COUNT 8
#define LPC_GPIO_P1_COUNT 24
#define LPC_GPIO_P2_COUNT 13
@@ -564,6 +566,8 @@
#define LPC_GPIO_P3_OUTP_SET 0x04
#define LPC_GPIO_P3_OUTP_CLR 0x08
#define LPC_GPIO_P3_OUTP_STATE 0x0c
+#define LPC_GPIO_SIZE 0x80
+
/* Aliases for logical pin numbers: */
#define LPC_GPIO_GPI_00(_n) (0 + _n)
#define LPC_GPIO_GPI_15(_n) (10 + _n)
Modified: head/sys/dev/uart/uart_dev_lpc.c
==============================================================================
--- head/sys/dev/uart/uart_dev_lpc.c Sun Jan 5 17:33:10 2014
(r260325)
+++ head/sys/dev/uart/uart_dev_lpc.c Sun Jan 5 18:40:06 2014
(r260326)
@@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
#include <sys/bus.h>
#include <sys/conf.h>
#include <machine/bus.h>
+#include <machine/fdt.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
@@ -43,16 +44,13 @@ __FBSDID("$FreeBSD$");
#include "uart_if.h"
#define DEFAULT_RCLK (13 * 1000 * 1000)
-#define LPC_UART_NO(_bas) (((_bas->bsh) - LPC_UART_BASE) >> 15)
-#define lpc_ns8250_get_auxreg(_bas, _reg) \
- bus_space_read_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg)
-#define lpc_ns8250_set_auxreg(_bas, _reg, _val) \
- bus_space_write_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg, _val);
+static bus_space_handle_t bsh_clkpwr;
+
#define lpc_ns8250_get_clkreg(_bas, _reg) \
- bus_space_read_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg))
+ bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg))
#define lpc_ns8250_set_clkreg(_bas, _reg, _val) \
- bus_space_write_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg), (_val))
+ bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val))
/*
* Clear pending interrupts. THRE is cleared by reading IIR. Data
@@ -293,9 +291,12 @@ lpc_ns8250_init(struct uart_bas *bas, in
u_long clkmode;
/* Enable UART clock */
- clkmode = lpc_ns8250_get_auxreg(bas, LPC_UART_CLKMODE);
- lpc_ns8250_set_auxreg(bas, LPC_UART_CLKMODE,
- clkmode | LPC_UART_CLKMODE_UART5(1));
+ bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0,
+ &bsh_clkpwr);
+ clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE);
+ lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode |
+ LPC_UART_CLKMODE_UART5(1));
+
#if 0
/* Work around H/W bug */
uart_setreg(bas, REG_DATA, 0x00);
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