Author: marius
Date: Tue Aug 6 15:34:11 2013
New Revision: 253994
URL: http://svnweb.freebsd.org/changeset/base/253994
Log:
Add MD (for now) atomic_store_acq_<type>() and use it in pmap_activate()
to get the semantics when setting the PMAP right. Prior to r251782, the
latter already used implicit acquire semantics, which - currently - means
to not employ additional explicit memory barriers under the hood (see also
r225889).
Modified:
head/sys/sparc64/include/atomic.h
head/sys/sparc64/sparc64/pmap.c
Modified: head/sys/sparc64/include/atomic.h
==============================================================================
--- head/sys/sparc64/include/atomic.h Tue Aug 6 14:41:41 2013
(r253993)
+++ head/sys/sparc64/include/atomic.h Tue Aug 6 15:34:11 2013
(r253994)
@@ -133,14 +133,14 @@
t; \
})
-#define atomic_load_acq(p, sz) ({
\
+#define atomic_ld_acq(p, sz) ({
\
itype(sz) v; \
v = atomic_cas((p), 0, 0, sz); \
__compiler_membar(); \
v; \
})
-#define atomic_load_clear(p, sz) ({
\
+#define atomic_ld_clear(p, sz) ({
\
itype(sz) e, r; \
for (e = *(volatile itype(sz) *)(p);; e = r) { \
r = atomic_cas((p), e, 0, sz); \
@@ -150,9 +150,8 @@
e; \
})
-#define atomic_store_rel(p, v, sz) do {
\
+#define atomic_st(p, v, sz) do {
\
itype(sz) e, r; \
- membar(LoadStore | StoreStore); \
for (e = *(volatile itype(sz) *)(p);; e = r) { \
r = atomic_cas((p), e, (v), sz); \
if (r == e) \
@@ -160,6 +159,16 @@
} \
} while (0)
+#define atomic_st_acq(p, v, sz) do {
\
+ atomic_st((p), (v), sz); \
+ __compiler_membar(); \
+} while (0)
+
+#define atomic_st_rel(p, v, sz) do {
\
+ membar(LoadStore | StoreStore); \
+ atomic_st((p), (v), sz); \
+} while (0)
+
#define ATOMIC_GEN(name, ptype, vtype, atype, sz)
\
\
static __inline vtype \
@@ -224,7 +233,7 @@ atomic_load_acq_ ## name(volatile ptype
static __inline vtype \
atomic_readandclear_ ## name(volatile ptype p) \
{ \
- return ((vtype)atomic_load_clear((p), sz)); \
+ return ((vtype)atomic_ld_clear((p), sz)); \
} \
\
static __inline vtype \
@@ -260,9 +269,14 @@ atomic_subtract_rel_ ## name(volatile pt
} \
\
static __inline void \
+atomic_store_acq_ ## name(volatile ptype p, vtype v) \
+{ \
+ atomic_st_acq((p), (v), sz); \
+} \
+static __inline void \
atomic_store_rel_ ## name(volatile ptype p, vtype v) \
{ \
- atomic_store_rel((p), (v), sz); \
+ atomic_st_rel((p), (v), sz); \
}
ATOMIC_GEN(int, u_int *, u_int, u_int, 32);
@@ -284,8 +298,10 @@ ATOMIC_GEN(ptr, uintptr_t *, uintptr_t,
#undef atomic_op
#undef atomic_op_acq
#undef atomic_op_rel
-#undef atomic_load_acq
-#undef atomic_store_rel
-#undef atomic_load_clear
+#undef atomic_ld_acq
+#undef atomic_ld_clear
+#undef atomic_st
+#undef atomic_st_acq
+#undef atomic_st_rel
#endif /* !_MACHINE_ATOMIC_H_ */
Modified: head/sys/sparc64/sparc64/pmap.c
==============================================================================
--- head/sys/sparc64/sparc64/pmap.c Tue Aug 6 14:41:41 2013
(r253993)
+++ head/sys/sparc64/sparc64/pmap.c Tue Aug 6 15:34:11 2013
(r253994)
@@ -2245,7 +2245,7 @@ pmap_activate(struct thread *td)
pm->pm_context[curcpu] = context;
#ifdef SMP
CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active);
- atomic_store_rel_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
+ atomic_store_acq_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
#else
CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
PCPU_SET(pmap, pm);
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