On Tue, 1 Jan 2013 16:59:15 +1300
Andrew Turner <and...@fubar.geek.nz> wrote:
> On Mon, 31 Dec 2012 14:18:19 -0800
> Oleksandr Tymoshenko <go...@freebsd.org> wrote:
> > I think we can use RTL release field of Cache ID register to
> > determine actual hardware release
> > and act accordingly.
> >
> >
> Yes, that appears to be correct, I have committed the known values of
> the RTL release field, from the ARM documentation, in r244919. I can
> have a look at detecting which cache controller we are on and adjust
> our behaviour accordingly but won't have any hardware to test with
> until the end of the week.
I have this untested patch that should only enable the errata when we
detect it is required.
Andrew
Index: sys/arm/include/pl310.h
===================================================================
--- sys/arm/include/pl310.h (revision 244919)
+++ sys/arm/include/pl310.h (working copy)
@@ -131,6 +131,7 @@ struct pl310_softc {
void* sc_irq_h;
int sc_enabled;
struct mtx sc_mtx;
+ u_int sc_rtl_revision;
};
/**
Index: sys/arm/arm/pl310.c
===================================================================
--- sys/arm/arm/pl310.c (revision 244918)
+++ sys/arm/arm/pl310.c (working copy)
@@ -135,11 +135,12 @@ pl310_cache_sync(void)
return;
#ifdef PL310_ERRATA_753970
- /* Write uncached PL310 register */
- pl310_write4(pl310_softc, 0x740, 0xffffffff);
-#else
- pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
+ if (sc->sc_rtl_release == CACHE_ID_RELEASE_r3p0)
+ /* Write uncached PL310 register */
+ pl310_write4(pl310_softc, 0x740, 0xffffffff);
+ else
#endif
+ pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
}
@@ -152,13 +153,17 @@ pl310_wbinv_all(void)
PL310_LOCK(pl310_softc);
#ifdef PL310_ERRATA_727915
- platform_pl310_write_debug(pl310_softc, 3);
+ if (sc->sc_rtl_release == CACHE_ID_RELEASE_r2p0 ||
+ sc->sc_rtl_release == CACHE_ID_RELEASE_r3p0)
+ platform_pl310_write_debug(pl310_softc, 3);
#endif
pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask);
pl310_cache_sync();
#ifdef PL310_ERRATA_727915
- platform_pl310_write_debug(pl310_softc, 0);
+ if (sc->sc_rtl_release == CACHE_ID_RELEASE_r2p0 ||
+ sc->sc_rtl_release == CACHE_ID_RELEASE_r3p0)
+ platform_pl310_write_debug(pl310_softc, 0);
#endif
PL310_UNLOCK(pl310_softc);
}
@@ -182,27 +187,32 @@ pl310_wbinv_range(vm_paddr_t start, vm_s
#ifdef PL310_ERRATA_727915
- platform_pl310_write_debug(pl310_softc, 3);
+ if (sc->sc_rtl_release == CACHE_ID_RELEASE_r2p0 ||
+ sc->sc_rtl_release == CACHE_ID_RELEASE_r3p0)
+ platform_pl310_write_debug(pl310_softc, 3);
#endif
while (size > 0) {
#ifdef PL310_ERRATA_588369
- /*
- * Errata 588369 says that clean + inv may keep the
- * cache line if it was clean, the recommanded workaround
- * is to clean then invalidate the cache line, with
- * write-back and cache linefill disabled
- */
-
- pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
- pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
-#else
- pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA, start);
+ if (sc->sc_rtl_release <= CACHE_ID_RELEASE_r1p0) {
+ /*
+ * Errata 588369 says that clean + inv may keep the
+ * cache line if it was clean, the recommanded
+ * workaround is to clean then invalidate the cache
+ * line, with write-back and cache linefill disabled.
+ */
+ pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start);
+ pl310_write4(pl310_softc, PL310_INV_LINE_PA, start);
+ } else
#endif
+ pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA,
+ start);
start += g_l2cache_line_size;
size -= g_l2cache_line_size;
}
#ifdef PL310_ERRATA_727915
- platform_pl310_write_debug(pl310_softc, 0);
+ if (sc->sc_rtl_release == CACHE_ID_RELEASE_r2p0 ||
+ sc->sc_rtl_release == CACHE_ID_RELEASE_r3p0)
+ platform_pl310_write_debug(pl310_softc, 0);
#endif
pl310_cache_sync();
@@ -307,6 +317,8 @@ pl310_attach(device_t dev)
pl310_filter, NULL, sc, &sc->sc_irq_h);
cache_id = pl310_read4(sc, PL310_CACHE_ID);
+ sc->sc_rtl_release = (cache_id >> CACHE_ID_RELEASE_SHIFT) &
+ CACHE_ID_RELEASE_MASK;
device_printf(dev, "Part number: 0x%x, release: 0x%x\n",
(cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK,
(cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK);
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