Author: adrian
Date: Sun Jun 17 05:56:27 2012
New Revision: 237184
URL: http://svn.freebsd.org/changeset/base/237184
Log:
AR9287 tidyups:
* Add an OS_A_REG_WRITE() routine - analog writes require a 100usec delay
on AR9280 and later, so create a method to do it.
* Use it for the AR9287 analog writes.
* Re-indent and style(9) the code.
Modified:
head/sys/dev/ath/ath_hal/ah_internal.h
head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c
Modified: head/sys/dev/ath/ath_hal/ah_internal.h
==============================================================================
--- head/sys/dev/ath/ath_hal/ah_internal.h Sun Jun 17 05:34:41 2012
(r237183)
+++ head/sys/dev/ath/ath_hal/ah_internal.h Sun Jun 17 05:56:27 2012
(r237184)
@@ -484,6 +484,8 @@ isBigEndian(void)
/* Analog register writes may require a delay between each one (eg Merlin?) */
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) <<
_f##_S) & (_f))) ; OS_DELAY(100); } while (0)
+#define OS_A_REG_WRITE(_a, _r, _v) \
+ do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
/* wait for the register contents to have the specified value */
extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c Sun Jun 17 05:34:41
2012 (r237183)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c Sun Jun 17 05:56:27
2012 (r237184)
@@ -45,70 +45,70 @@ static void
ar9287SetPowerCalTable(struct ath_hal *ah,
const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
{
- struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
- uint8_t *pCalBChans = NULL;
- uint16_t pdGainOverlap_t2;
- uint16_t numPiers = 0, i;
- uint16_t numXpdGain, xpdMask;
- uint16_t xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
- uint32_t regChainOffset;
+ struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
+ uint8_t *pCalBChans = NULL;
+ uint16_t pdGainOverlap_t2;
+ uint16_t numPiers = 0, i;
+ uint16_t numXpdGain, xpdMask;
+ uint16_t xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
+ uint32_t regChainOffset;
HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
- struct ar9287_eeprom *pEepData = &ee->ee_base;
+ struct ar9287_eeprom *pEepData = &ee->ee_base;
- xpdMask = pEepData->modalHeader.xpdGain;
+ xpdMask = pEepData->modalHeader.xpdGain;
- if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
- AR9287_EEP_MINOR_VER_2)
- pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
- else
- pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah,
AR_PHY_TPCRG5),
- AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
+ if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
+ AR9287_EEP_MINOR_VER_2)
+ pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
+ else
+ pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),
+ AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
/* Note: Kiwi should only be 2ghz.. */
- if (IEEE80211_IS_CHAN_2GHZ(chan)) {
- pCalBChans = pEepData->calFreqPier2G;
- numPiers = AR9287_NUM_2G_CAL_PIERS;
- pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287
*)pEepData->calPierData2G[0];
- AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
- }
- numXpdGain = 0;
-
- /* Calculate the value of xpdgains from the xpdGain Mask */
- for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
- if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
- if (numXpdGain >= AR5416_NUM_PD_GAINS)
- break;
- xpdGainValues[numXpdGain] =
- (uint16_t)(AR5416_PD_GAINS_IN_MASK-i);
- numXpdGain++;
- }
- }
-
- OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
- (numXpdGain - 1) & 0x3);
- OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
- xpdGainValues[0]);
- OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
- xpdGainValues[1]);
- OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
- xpdGainValues[2]);
-
- for (i = 0; i < AR9287_MAX_CHAINS; i++) {
- regChainOffset = i * 0x1000;
-
- if (pEepData->baseEepHeader.txMask & (1 << i)) {
- int8_t txPower;
- pRawDatasetOpenLoop =
- (struct cal_data_op_loop_ar9287
*)pEepData->calPierData2G[i];
- ar9287olcGetTxGainIndex(ah, chan,
- pRawDatasetOpenLoop,
- pCalBChans, numPiers,
- &txPower);
- ar9287olcSetPDADCs(ah, txPower, i);
- }
- }
+ if (IEEE80211_IS_CHAN_2GHZ(chan)) {
+ pCalBChans = pEepData->calFreqPier2G;
+ numPiers = AR9287_NUM_2G_CAL_PIERS;
+ pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287
*)pEepData->calPierData2G[0];
+ AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
+ }
+ numXpdGain = 0;
+
+ /* Calculate the value of xpdgains from the xpdGain Mask */
+ for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+ if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+ if (numXpdGain >= AR5416_NUM_PD_GAINS)
+ break;
+ xpdGainValues[numXpdGain] =
+ (uint16_t)(AR5416_PD_GAINS_IN_MASK-i);
+ numXpdGain++;
+ }
+ }
+
+ OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
+ (numXpdGain - 1) & 0x3);
+ OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
+ xpdGainValues[0]);
+ OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
+ xpdGainValues[1]);
+ OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
+ xpdGainValues[2]);
- *pTxPowerIndexOffset = 0;
+ for (i = 0; i < AR9287_MAX_CHAINS; i++) {
+ regChainOffset = i * 0x1000;
+
+ if (pEepData->baseEepHeader.txMask & (1 << i)) {
+ int8_t txPower;
+ pRawDatasetOpenLoop =
+ (struct cal_data_op_loop_ar9287
*)pEepData->calPierData2G[i];
+ ar9287olcGetTxGainIndex(ah, chan,
+ pRawDatasetOpenLoop,
+ pCalBChans, numPiers,
+ &txPower);
+ ar9287olcSetPDADCs(ah, txPower, i);
+ }
+ }
+
+ *pTxPowerIndexOffset = 0;
}
@@ -329,20 +329,20 @@ ar9287SetTransmitPower(struct ath_hal *a
const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
-#define N(a) (sizeof (a) / sizeof (a[0]))
+#define N(a) (sizeof (a) / sizeof (a[0]))
const struct modal_eep_ar9287_header *pModal;
struct ath_hal_5212 *ahp = AH5212(ah);
- int16_t ratesArray[Ar5416RateSize];
- int16_t txPowerIndexOffset = 0;
- uint8_t ht40PowerIncForPdadc = 2;
- int i;
-
- uint16_t cfgCtl;
- uint16_t powerLimit;
- uint16_t twiceAntennaReduction;
- uint16_t twiceMaxRegulatoryPower;
- int16_t maxPower;
+ int16_t ratesArray[Ar5416RateSize];
+ int16_t txPowerIndexOffset = 0;
+ uint8_t ht40PowerIncForPdadc = 2;
+ int i;
+
+ uint16_t cfgCtl;
+ uint16_t powerLimit;
+ uint16_t twiceAntennaReduction;
+ uint16_t twiceMaxRegulatoryPower;
+ int16_t maxPower;
HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
struct ar9287_eeprom *pEepData = &ee->ee_base;
@@ -351,7 +351,8 @@ ar9287SetTransmitPower(struct ath_hal *a
cfgCtl = ath_hal_getctl(ah, chan);
powerLimit = chan->ic_maxregpower * 2;
twiceAntennaReduction = chan->ic_maxantgain;
- twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER,
AH_PRIVATE(ah)->ah_powerLimit);
+ twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER,
+ AH_PRIVATE(ah)->ah_powerLimit);
pModal = &pEepData->modalHeader;
HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
__func__,chan->ic_freq, cfgCtl );
@@ -361,9 +362,9 @@ ar9287SetTransmitPower(struct ath_hal *a
/* Fetch per-rate power table for the given channel */
if (! ar9287SetPowerPerRateTable(ah, pEepData, chan,
- &ratesArray[0],cfgCtl,
- twiceAntennaReduction,
- twiceMaxRegulatoryPower, powerLimit)) {
+ &ratesArray[0],cfgCtl,
+ twiceAntennaReduction,
+ twiceMaxRegulatoryPower, powerLimit)) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: unable to set tx power per rate table\n", __func__);
return AH_FALSE;
@@ -476,7 +477,8 @@ ar9287SetBoardValues(struct ath_hal *ah,
pModal->antCtrlChain[i]);
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) + regChainOffset,
- (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0) +
regChainOffset)
+ (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)
+ + regChainOffset)
& ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
SM(pModal->iqCalICh[i],
@@ -500,7 +502,6 @@ ar9287SetBoardValues(struct ath_hal *ah,
pModal->rxTxMarginCh[i]);
}
-
if (IEEE80211_IS_CHAN_HT40(chan))
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
@@ -539,8 +540,8 @@ ar9287SetBoardValues(struct ath_hal *ah,
SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
- OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
- OS_DELAY(100); /* analog write */
+ /* Analog write - requires a 100usec delay */
+ OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH0, regval);
regval = OS_REG_READ(ah, AR9287_AN_RF2G3_CH1);
regval &= ~(AR9287_AN_RF2G3_DB1 |
@@ -556,8 +557,7 @@ ar9287SetBoardValues(struct ath_hal *ah,
SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
- OS_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
- OS_DELAY(100); /* analog write */
+ OS_A_REG_WRITE(ah, AR9287_AN_RF2G3_CH1, regval);
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
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