Author: adrian
Date: Sun Jun 17 04:48:47 2012
New Revision: 237182
URL: http://svn.freebsd.org/changeset/base/237182
Log:
Bring over the AR9285 specific PCIe suspend/resume/ASPM workarounds.
Obtained from: Qualcomm Atheros, Linux ath9k
Modified:
head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Sun Jun 17 03:59:17
2012 (r237181)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Sun Jun 17 04:48:47
2012 (r237182)
@@ -367,18 +367,71 @@ bad:
static void
ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
+ uint32_t val;
+
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
+ }
+
+ /*
+ * Set PCIe workaround bits
+ *
+ * NOTE:
+ *
+ * In Merlin and Kite, bit 14 in WA register (disable L1) should only
+ * be set when device enters D3 and be cleared when device comes back
+ * to D0.
+ */
+ if (power_off) { /* Power-off */
+ OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+
+ val = OS_REG_READ(ah, AR_WA);
+
+ /*
+ * Disable bit 6 and 7 before entering D3 to prevent
+ * system hang.
+ */
+ val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
+
+ /*
+ * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
+ *
+ * XXX The reference HAL does it this way - it only sets
+ * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
+ * which it (currently) isn't. So the following statement
+ * is currently a NOP.
+ */
+ if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
+ val |= AR_WA_D3_L1_DISABLE;
+
+ if (AR_SREV_9285E_20(ah))
+ val |= AR_WA_BIT23;
+
+ OS_REG_WRITE(ah, AR_WA, val);
+ } else { /* Power-on */
+ val = AR9285_WA_DEFAULT;
+ /*
+ * See note above: make sure L1_DISABLE is not set.
+ */
+ val &= (~AR_WA_D3_L1_DISABLE);
+
+ /* Software workaroud for ASPM system hang. */
+ val |= (AR_WA_BIT6 | AR_WA_BIT7);
+
+ if (AR_SREV_9285E_20(ah))
+ val |= AR_WA_BIT23;
+
+ OS_REG_WRITE(ah, AR_WA, val);
+
+ /* set bit 19 to allow forcing of pcie core into L1 state */
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
- OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
}
}
static void
ar9285DisablePCIE(struct ath_hal *ah)
{
- /* XXX TODO */
}
static void
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