Author: jchandra
Date: Mon Nov 21 08:12:36 2011
New Revision: 227783
URL: http://svn.freebsd.org/changeset/base/227783
Log:
Merge XLP 3XX updates and related rework.
* Update message station (CMS) code, read queue ids from PCI header.
* Use interrupts to wakeup message handling threads on 3XX
* Update PIC code, read interrupt information from PCI header instead
of using fixed values.
* Update PCI interrupt handling for the PIC change.
* Update code for getting chip frequency, new code support XLP 3XX
* Misc style(9) fixes
In collaboration with: prabhath at netlogicmicro com (CMS/PIC)
venkatesh at netlogicmicro.com (PCI)
Added:
head/sys/mips/nlm/hal/nlm_hal.c (contents, props changed)
Modified:
head/sys/mips/nlm/cms.c
head/sys/mips/nlm/files.xlp
head/sys/mips/nlm/hal/cop2.h
head/sys/mips/nlm/hal/fmn.c
head/sys/mips/nlm/hal/fmn.h
head/sys/mips/nlm/hal/iomap.h
head/sys/mips/nlm/hal/pcibus.h
head/sys/mips/nlm/hal/pic.h
head/sys/mips/nlm/msgring.h
head/sys/mips/nlm/xlp.h
head/sys/mips/nlm/xlp_machdep.c
head/sys/mips/nlm/xlp_pci.c
Modified: head/sys/mips/nlm/cms.c
==============================================================================
--- head/sys/mips/nlm/cms.c Mon Nov 21 07:55:37 2011 (r227782)
+++ head/sys/mips/nlm/cms.c Mon Nov 21 08:12:36 2011 (r227783)
@@ -75,8 +75,8 @@ __FBSDID("$FreeBSD$");
* load
*/
struct msgring_thread {
- struct thread *thread; /* msgring handler threads */
- int needed; /* thread needs to wake up */
+ struct thread *thread; /* msgring handler threads */
+ int needed; /* thread needs to wake up */
};
static struct msgring_thread msgring_threads[XLP_MAX_CORES * XLP_MAX_THREADS];
static struct proc *msgring_proc; /* all threads are under a proc */
@@ -91,142 +91,80 @@ struct tx_stn_handler {
};
static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS];
static struct mtx msgmap_lock;
-uint64_t xlp_cms_base;
uint32_t xlp_msg_thread_mask;
-static int xlp_msg_threads_per_core = 3; /* Make tunable */
+static int xlp_msg_threads_per_core = 3;
static void create_msgring_thread(int hwtid);
static int msgring_process_fast_intr(void *arg);
-/*
- * Boot time init, called only once
- */
-void
-xlp_msgring_config(void)
-{
- unsigned int thrmask, mask;
- int i;
-
- /* TODO: Add other nodes */
- xlp_cms_base = nlm_get_cms_regbase(0);
-
- mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
- if (xlp_threads_per_core < xlp_msg_threads_per_core)
- xlp_msg_threads_per_core = xlp_threads_per_core;
- thrmask = ((1 << xlp_msg_threads_per_core) - 1);
- /*thrmask <<= xlp_threads_per_core - xlp_msg_threads_per_core;*/
- mask = 0;
- for (i = 0; i < XLP_MAX_CORES; i++) {
- mask <<= XLP_MAX_THREADS;
- mask |= thrmask;
- }
- xlp_msg_thread_mask = xlp_hw_thread_mask & mask;
- printf("Initializing CMS...@%jx, Message handler thread mask %#jx\n",
- (uintmax_t)xlp_cms_base, (uintmax_t)xlp_msg_thread_mask);
-}
-/*
- * Initialize the messaging subsystem.
- *
- * Message Stations are shared among all threads in a cpu core, this
- * has to be called once from every core which is online.
+/* Debug counters */
+static int msgring_nintr[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int msgring_wakeup_sleep[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int msgring_wakeup_nosleep[XLP_MAX_CORES * XLP_MAX_THREADS];
+static int fmn_msgcount[XLP_MAX_CORES * XLP_MAX_THREADS][4];
+static int fmn_loops[XLP_MAX_CORES * XLP_MAX_THREADS];
+
+/* Whether polled driver implementation */
+static int polled = 1;
+
+/* We do only i/o device credit setup here. CPU credit setup is now
+ * moved to xlp_msgring_cpu_init() so that the credits get setup
+ * only if the CPU exists. xlp_msgring_cpu_init() gets called from
+ * platform_init_ap; and this makes it easy for us to setup CMS
+ * credits for various types of XLP chips, with varying number of
+ * cpu's and cores.
*/
-void
-xlp_msgring_iodi_config(void)
-{
- void *cookie;
-
- xlp_msgring_config();
-/* nlm_cms_default_setup(0,0,0,0); */
- nlm_cms_credit_setup(50);
- create_msgring_thread(0);
- cpu_establish_hardintr("msgring", msgring_process_fast_intr, NULL,
- NULL, IRQ_MSGRING, INTR_TYPE_NET, &cookie);
-}
-
-void
-nlm_cms_credit_setup(int credit)
+static void
+xlp_cms_credit_setup(int credit)
{
+ uint64_t cmspcibase, cmsbase, pcibase;
+ uint32_t devoffset;
+ int dev, fn, maxqid;
int src, qid, i;
-#if 0
- /* there are a total of 18 src stations on XLP. */
- printf("Setting up CMS credits!\n");
- for (src=0; src<18; src++) {
- for(qid=0; qid<1024; qid++) {
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
- }
- }
+ for (i = 0; i < XLP_MAX_NODES; i++) {
+ cmspcibase = nlm_get_cms_pcibase(i);
+ if (!nlm_dev_exists(XLP_IO_CMS_OFFSET(i)))
+ continue;
+ cmsbase = nlm_get_cms_regbase(i);
+ maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0);
+ for (dev = 0; dev < 8; dev++) {
+ for (fn = 0; fn < 8; fn++) {
+ devoffset = XLP_HDR_OFFSET(i, 0, dev, fn);
+ if (nlm_dev_exists(devoffset) == 0)
+ continue;
+ pcibase = nlm_pcicfg_base(devoffset);
+ src = nlm_qidstart(pcibase);
+ if (src == 0)
+ continue;
+#if 0 /* Debug */
+ printf("Setup CMS credits for queues ");
+ printf("[%d to %d] from src %d\n", 0,
+ maxqid, src);
#endif
- printf("Setting up CMS credits!\n");
- /* CPU Credits */
- for (i = 1; i < 8; i++) {
- src = (i << 4);
- for (qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
- }
- /* PCIE Credits */
- for(i = 0; i < 4; i++) {
- src = (256 + (i * 2));
- for(qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
- }
- /* DTE Credits */
- src = 264;
- for (qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
- /* RSA Credits */
- src = 272;
- for (qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
-
- /* Crypto Credits */
- src = 281;
- for (qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
-
- /* CMP Credits */
- src = 298;
- for (qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
-
- /* POE Credits */
- src = 384;
- for(qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
-
- /* NAE Credits */
- src = 476;
- for(qid = 0; qid < 1024; qid++)
- nlm_cms_setup_credits(xlp_cms_base, qid, src, credit);
-}
-
-void
-xlp_msgring_cpu_init(uint32_t cpuid)
-{
- int queue,i;
-
- queue = CMS_CPU_PUSHQ(0, ((cpuid >> 2) & 0x7), (cpuid & 0x3), 0);
- /* temp allocate 4 segments to each output queue */
- nlm_cms_alloc_onchip_q(xlp_cms_base, queue, 4);
- /* Enable high watermark and non empty interrupt */
- nlm_cms_per_queue_level_intr(xlp_cms_base, queue,2,0);
- for(i=0;i<8;i++) {
- /* temp distribute the credits to all CPU stations */
- nlm_cms_setup_credits(xlp_cms_base, queue, i * 16, 8);
+ for (qid = 0; qid < maxqid; qid++)
+ nlm_cms_setup_credits(cmsbase, qid,
+ src, credit);
+ }
+ }
}
}
void
-xlp_cpu_msgring_handler(int bucket, int size, int code, int stid,
- struct nlm_fmn_msg *msg, void *data)
+xlp_msgring_cpu_init(int node, int cpu, int credit)
{
- int i;
-
- printf("vc:%d srcid:%d size:%d\n",bucket,stid,size);
- for(i=0;i<size;i++) {
- printf("msg->msg[%d]:0x%jx ", i, (uintmax_t)msg->msg[i]);
+ uint64_t cmspcibase = nlm_get_cms_pcibase(node);
+ uint64_t cmsbase = nlm_get_cms_regbase(node);
+ int qid, maxqid, src;
+
+ maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0);
+
+ /* cpu credit setup is done only from thread-0 of each core */
+ if((cpu % 4) == 0) {
+ src = cpu << 2; /* each thread has 4 vc's */
+ for (qid = 0; qid < maxqid; qid++)
+ nlm_cms_setup_credits(cmsbase, qid, src, credit);
}
- printf("\n");
}
/*
@@ -234,35 +172,100 @@ xlp_cpu_msgring_handler(int bucket, int
* Use max_msgs = 0 to drain out all messages.
*/
int
-xlp_handle_msg_vc(int vc, int max_msgs)
+xlp_handle_msg_vc(u_int vcmask, int max_msgs)
{
struct nlm_fmn_msg msg;
- int i, srcid = 0, size = 0, code = 0;
+ int srcid = 0, size = 0, code = 0;
struct tx_stn_handler *he;
uint32_t mflags, status;
+ int n_msgs = 0, vc, m, hwtid;
+ u_int msgmask;
- for (i = 0; i < max_msgs; i++) {
+
+ hwtid = nlm_cpuid();
+ for (;;) {
+ /* check if VC empty */
mflags = nlm_save_flags_cop2();
- status = nlm_fmn_msgrcv(vc, &srcid, &size, &code, &msg);
+ status = nlm_read_c2_msgstatus1();
nlm_restore_flags(mflags);
- if (status != 0) /* If there is no msg or error */
- break;
- if (srcid < 0 && srcid >= 1024) {
- printf("[%s]: bad src id %d\n", __func__, srcid);
- continue;
- }
- he = &msgmap[srcid];
- if(he->action != NULL)
- (he->action)(vc, size, code, srcid, &msg, he->arg);
-#if 0 /* debug */
- else
- printf("[%s]: No Handler for message from stn_id=%d,"
- " vc=%d, size=%d, msg0=%jx, dropping message\n",
- __func__, srcid, vc, size, (uintmax_t)msg.msg[0]);
+
+ msgmask = ((status >> 24) & 0xf) ^ 0xf;
+ msgmask &= vcmask;
+ if (msgmask == 0)
+ break;
+ m = 0;
+ for (vc = 0; vc < 4; vc++) {
+ if ((msgmask & (1 << vc)) == 0)
+ continue;
+
+ mflags = nlm_save_flags_cop2();
+ status = nlm_fmn_msgrcv(vc, &srcid, &size, &code,
+ &msg);
+ nlm_restore_flags(mflags);
+ if (status != 0) /* no msg or error */
+ continue;
+ if (srcid < 0 && srcid >= 1024) {
+ printf("[%s]: bad src id %d\n", __func__,
+ srcid);
+ continue;
+ }
+ he = &msgmap[srcid];
+ if(he->action != NULL)
+ (he->action)(vc, size, code, srcid, &msg,
he->arg);
+#if 1 /* defined DEBUG */
+ else
+ printf("[%s]: No Handler for msg from stn %d,"
+ " vc=%d, size=%d, msg0=%jx, droppinge\n",
+ __func__, srcid, vc, size,
+ (uintmax_t)msg.msg[0]);
#endif
+ fmn_msgcount[hwtid][vc] += 1;
+ m++; /* msgs handled in this iter */
+ }
+ if (m == 0)
+ break; /* nothing done in this iter */
+ n_msgs += m;
+ if (max_msgs > 0 && n_msgs >= max_msgs)
+ break;
}
- return (i);
+ return (n_msgs);
+}
+
+static void
+xlp_discard_msg_vc(u_int vcmask)
+{
+ struct nlm_fmn_msg msg;
+ int srcid = 0, size = 0, code = 0, vc;
+ uint32_t mflags, status;
+
+ for (vc = 0; vc < 4; vc++) {
+ for (;;) {
+ mflags = nlm_save_flags_cop2();
+ status = nlm_fmn_msgrcv(vc, &srcid,
+ &size, &code, &msg);
+ nlm_restore_flags(mflags);
+
+ /* break if there is no msg or error */
+ if (status != 0)
+ break;
+ }
+ }
+}
+
+void
+xlp_cms_enable_intr(int node, int cpu, int type, int watermark)
+{
+ uint64_t cmsbase;
+ int i, qid;
+
+ cmsbase = nlm_get_cms_regbase(node);
+
+ for (i = 0; i < 4; i++) {
+ qid = (i + (cpu * 4)) & 0x7f;
+ nlm_cms_per_queue_level_intr(cmsbase, qid, type, watermark);
+ nlm_cms_per_queue_timer_intr(cmsbase, qid, 0x1, 0);
+ }
}
static int
@@ -274,6 +277,7 @@ msgring_process_fast_intr(void *arg)
cpu = nlm_cpuid();
mthd = &msgring_threads[cpu];
+ msgring_nintr[cpu]++;
td = mthd->thread;
/* clear pending interrupts */
@@ -283,24 +287,24 @@ msgring_process_fast_intr(void *arg)
mthd->needed = 1;
thread_lock(td);
if (TD_AWAITING_INTR(td)) {
+ msgring_wakeup_sleep[cpu]++;
TD_CLR_IWAIT(td);
sched_add(td, SRQ_INTR);
- }
+ } else
+ msgring_wakeup_nosleep[cpu]++;
thread_unlock(td);
+
return (FILTER_HANDLED);
}
-u_int fmn_msgcount[32][4];
-u_int fmn_loops[32];
-
static void
msgring_process(void * arg)
{
volatile struct msgring_thread *mthd;
struct thread *td;
- uint32_t mflags;
- int hwtid, vc, handled, nmsgs;
+ uint32_t mflags, msgstatus1;
+ int hwtid, nmsgs;
hwtid = (intptr_t)arg;
mthd = &msgring_threads[hwtid];
@@ -314,39 +318,47 @@ msgring_process(void * arg)
thread_unlock(td);
if (hwtid != nlm_cpuid())
- printf("Misscheduled hwtid %d != cpuid %d\n", hwtid,
nlm_cpuid());
- mflags = nlm_save_flags_cop2();
- nlm_fmn_cpu_init(IRQ_MSGRING, 0, 0, 0, 0, 0);
- nlm_restore_flags(mflags);
+ printf("Misscheduled hwtid %d != cpuid %d\n", hwtid,
+ nlm_cpuid());
- /* start processing messages */
- for( ; ; ) {
- /*atomic_store_rel_int(&mthd->needed, 0);*/
+ xlp_discard_msg_vc(0xf);
+ xlp_msgring_cpu_init(nlm_nodeid(), nlm_cpuid(), CMS_DEFAULT_CREDIT);
+ if (polled == 0) {
+ mflags = nlm_save_flags_cop2();
+ nlm_fmn_cpu_init(IRQ_MSGRING, 0, 0, 0, 0, 0);
+ nlm_restore_flags(mflags);
+ xlp_cms_enable_intr(nlm_nodeid(), nlm_cpuid(), 0x2, 0);
+ /* clear pending interrupts.
+ * they will get re-raised if still valid */
+ nlm_write_c0_eirr(1ULL << IRQ_MSGRING);
+ }
- /* enable cop2 access */
- do {
- handled = 0;
- for (vc = 0; vc < 4; vc++) {
- nmsgs = xlp_handle_msg_vc(vc, 1);
- fmn_msgcount[hwtid][vc] += nmsgs;
- handled += nmsgs;
- }
- } while (handled);
+ /* start processing messages */
+ for (;;) {
+ atomic_store_rel_int(&mthd->needed, 0);
+ nmsgs = xlp_handle_msg_vc(0xf, 0);
/* sleep */
-#if 0
- thread_lock(td);
- if (mthd->needed) {
+ if (polled == 0) {
+ /* clear VC-pend bits */
+ mflags = nlm_save_flags_cop2();
+ msgstatus1 = nlm_read_c2_msgstatus1();
+ msgstatus1 |= (0xf << 16);
+ nlm_write_c2_msgstatus1(msgstatus1);
+ nlm_restore_flags(mflags);
+
+ thread_lock(td);
+ if (mthd->needed) {
+ thread_unlock(td);
+ continue;
+ }
+ sched_class(td, PRI_ITHD);
+ TD_SET_IWAIT(td);
+ mi_switch(SW_VOL, NULL);
thread_unlock(td);
- continue;
- }
- sched_class(td, PRI_ITHD);
- TD_SET_IWAIT(td);
- mi_switch(SW_VOL, NULL);
- thread_unlock(td);
-#else
- pause("wmsg", 1);
-#endif
+ } else
+ pause("wmsg", 1);
+
fmn_loops[hwtid]++;
}
}
@@ -370,7 +382,9 @@ create_msgring_thread(int hwtid)
sched_class(td, PRI_ITHD);
sched_add(td, SRQ_INTR);
thread_unlock(td);
- CTR2(KTR_INTR, "%s: created %s", __func__, td->td_name);
+ if (bootverbose)
+ printf("Msgring handler create on cpu %d (%s)\n",
+ hwtid, td->td_name);
}
int
@@ -381,7 +395,7 @@ register_msgring_handler(int startb, int
printf("Register handler %d-%d %p(%p)\n", startb, endb, action, arg);
KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS,
- ("Invalid value for for bucket range %d,%d", startb, endb));
+ ("Invalid value for bucket range %d,%d", startb, endb));
mtx_lock_spin(&msgmap_lock);
for (i = startb; i <= endb; i++) {
@@ -395,6 +409,45 @@ register_msgring_handler(int startb, int
}
/*
+ * Initialize the messaging subsystem.
+ *
+ * Message Stations are shared among all threads in a cpu core, this
+ * has to be called once from every core which is online.
+ */
+static void
+xlp_msgring_config(void *arg)
+{
+ void *cookie;
+ unsigned int thrmask, mask;
+ int i;
+
+ mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
+ if (xlp_threads_per_core < xlp_msg_threads_per_core)
+ xlp_msg_threads_per_core = xlp_threads_per_core;
+ thrmask = ((1 << xlp_msg_threads_per_core) - 1);
+ /*thrmask <<= xlp_threads_per_core - xlp_msg_threads_per_core;*/
+ mask = 0;
+ for (i = 0; i < XLP_MAX_CORES; i++) {
+ mask <<= XLP_MAX_THREADS;
+ mask |= thrmask;
+ }
+ xlp_msg_thread_mask = xlp_hw_thread_mask & mask;
+#if 0
+ printf("CMS Message handler thread mask %#jx\n",
+ (uintmax_t)xlp_msg_thread_mask);
+#endif
+
+ if (nlm_is_xlp3xx())
+ polled = 0; /* switch to interrupt driven driver */
+
+/* nlm_cms_default_setup(0,0,0,0); */
+ xlp_cms_credit_setup(CMS_DEFAULT_CREDIT);
+ create_msgring_thread(0);
+ cpu_establish_hardintr("msgring", msgring_process_fast_intr, NULL,
+ NULL, IRQ_MSGRING, INTR_TYPE_NET, &cookie);
+}
+
+/*
* Start message ring processing threads on other CPUs, after SMP start
*/
static void
@@ -409,6 +462,8 @@ start_msgring_threads(void *arg)
}
}
+SYSINIT(xlp_msgring_config, SI_SUB_DRIVERS, SI_ORDER_FIRST,
+ xlp_msgring_config, NULL);
SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE,
start_msgring_threads, NULL);
Modified: head/sys/mips/nlm/files.xlp
==============================================================================
--- head/sys/mips/nlm/files.xlp Mon Nov 21 07:55:37 2011 (r227782)
+++ head/sys/mips/nlm/files.xlp Mon Nov 21 08:12:36 2011 (r227783)
@@ -1,4 +1,5 @@
# $FreeBSD$
+mips/nlm/hal/nlm_hal.c standard
mips/nlm/hal/fmn.c standard
mips/nlm/xlp_machdep.c standard
mips/nlm/intr_machdep.c standard
Modified: head/sys/mips/nlm/hal/cop2.h
==============================================================================
--- head/sys/mips/nlm/hal/cop2.h Mon Nov 21 07:55:37 2011
(r227782)
+++ head/sys/mips/nlm/hal/cop2.h Mon Nov 21 08:12:36 2011
(r227783)
@@ -38,7 +38,7 @@
#define COP2_RXMSGSTATUS 3
#define COP2_MSGSTATUS1 4
#define COP2_MSGCONFIG 5
-#define COP2_MSGCONFIG1 6
+#define COP2_MSGERROR 6
#define CROSSTHR_POPQ_EN 0x01
#define VC0_POPQ_EN 0x02
@@ -160,7 +160,10 @@ NLM_DEFINE_COP2_ACCESSORS32(txmsgstatus,
NLM_DEFINE_COP2_ACCESSORS32(rxmsgstatus, COP2_RXMSGSTATUS, 0);
NLM_DEFINE_COP2_ACCESSORS32(msgstatus1, COP2_MSGSTATUS1, 0);
NLM_DEFINE_COP2_ACCESSORS32(msgconfig, COP2_MSGCONFIG, 0);
-NLM_DEFINE_COP2_ACCESSORS32(msgconfig1, COP2_MSGCONFIG1, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror0, COP2_MSGERROR, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror1, COP2_MSGERROR, 1);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror2, COP2_MSGERROR, 2);
+NLM_DEFINE_COP2_ACCESSORS32(msgerror3, COP2_MSGERROR, 3);
/* successful completion returns 1, else 0 */
static inline int
@@ -279,7 +282,7 @@ nlm_fmn_msgrcv(int vc, int *srcid, int *
}
static inline void
-nlm_fmn_cpu_init(int int_vec, int ctpe, int v0pe, int v1pe, int v2pe, int v3pe)
+nlm_fmn_cpu_init(int int_vec, int ecc_en, int v0pe, int v1pe, int v2pe, int
v3pe)
{
uint32_t val = nlm_read_c2_msgconfig();
@@ -287,12 +290,12 @@ nlm_fmn_cpu_init(int int_vec, int ctpe,
* in msgconfig register of cop2.
* As per chip/cpu RTL, [16:20] bits consist of int_vec.
*/
- val |= ((int_vec & 0x1f) << 16) |
+ val |= (((int_vec & 0x1f) << 16) |
+ ((ecc_en & 0x1) << 8) |
((v3pe & 0x1) << 4) |
((v2pe & 0x1) << 3) |
((v1pe & 0x1) << 2) |
- ((v0pe & 0x1) << 1) |
- (ctpe & 0x1);
+ ((v0pe & 0x1) << 1));
nlm_write_c2_msgconfig(val);
}
Modified: head/sys/mips/nlm/hal/fmn.c
==============================================================================
--- head/sys/mips/nlm/hal/fmn.c Mon Nov 21 07:55:37 2011 (r227782)
+++ head/sys/mips/nlm/hal/fmn.c Mon Nov 21 08:12:36 2011 (r227783)
@@ -67,7 +67,6 @@ uint64_t nlm_cms_spill_total_messages =
* For all 4 nodes, there are 18*4 = 72 FMN stations
*/
uint32_t nlm_cms_total_stations = 18 * 4 /*xlp_num_nodes*/;
-uint32_t cms_onchip_seg_availability[CMS_ON_CHIP_PER_QUEUE_SPACE];
/**
* Takes inputs as node, queue_size and maximum number of queues.
@@ -146,114 +145,6 @@ void nlm_cms_setup_credits(uint64_t base
}
-int nlm_cms_config_onchip_queue (uint64_t base, uint64_t spill_base,
- int qid, int spill_en)
-{
-
- /* Configure 32 as onchip queue depth */
- nlm_cms_alloc_onchip_q(base, qid, 1);
-
- /* Spill configuration */
- if (spill_en) {
- /* Configure 4*4KB = 16K as spill size */
- nlm_cms_alloc_spill_q(base, qid, spill_base, 4);
- }
-
-#if 0
- /* configure credits for src cpu0, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU0_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu1, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU1_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu2, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU2_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu3, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU3_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu4, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU4_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu5, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU5_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu6, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU6_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cpu7, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CPU7_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src pcie0, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_PCIE0_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src pcie1, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_PCIE1_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src pcie2, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_PCIE2_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src pcie3, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_PCIE3_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src dte, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_DTE_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src rsa_ecc, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_RSA_ECC_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src crypto, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CRYPTO_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src cmp, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_CMP_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src poe, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_POE_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-
- /* configure credits for src nae, on this queue */
- nlm_cms_setup_credits(base, qid, CMS_NAE_SRC_STID,
- CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
- nlm_cms_spill_total_messages));
-#endif
-
- return 0;
-}
-
/*
* base - CMS module base address for this node.
* qid - is the output queue id otherwise called as vc id
@@ -268,7 +159,7 @@ int nlm_cms_alloc_spill_q(uint64_t base,
uint64_t queue_config;
uint32_t spill_start;
- if(nsegs > CMS_MAX_SPILL_SEGMENTS_PER_QUEUE) {
+ if (nsegs > CMS_MAX_SPILL_SEGMENTS_PER_QUEUE) {
return 1;
}
@@ -286,152 +177,6 @@ int nlm_cms_alloc_spill_q(uint64_t base,
return 0;
}
-/*
- * base - CMS module base address for this node.
- * qid - is the output queue id otherwise called as vc id
- * nsegs - No of segments where a "1" indicates 32 credits. On chip
- * credits must be a multiple of 32.
- */
-int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs)
-{
- static uint32_t curr_end = 0;
- uint64_t queue_config;
- int onchipbase, start, last;
- uint8_t i;
-
- if( ((curr_end + nsegs) > CMS_MAX_ONCHIP_SEGMENTS) ||
- (nsegs > CMS_ON_CHIP_PER_QUEUE_SPACE) ) {
- /* Invalid configuration */
- return 1;
- }
- if(((curr_end % 32) + nsegs - 1) <= 31) {
- onchipbase = (curr_end / 32);
- start = (curr_end % 32);
- curr_end += nsegs;
- } else {
- onchipbase = (curr_end / 32) + 1;
- start = 0;
- curr_end = ((onchipbase * 32) + nsegs);
- }
- last = start + nsegs - 1;
-
- for(i = start;i <= last;i++) {
- if(cms_onchip_seg_availability[onchipbase] & (1 << i)) {
- /* Conflict!!! segment is already allocated */
- return 1;
- }
- }
- /* Update the availability bitmap as consumed */
- for(i = start; i <= last; i++) {
- cms_onchip_seg_availability[onchipbase] |= (1 << i);
- }
-
- queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
-
- /* On chip configuration */
- queue_config = (((uint64_t)CMS_QUEUE_ENA << 63) |
- ((onchipbase & 0x1f) << 10) |
- ((last & 0x1f) << 5) |
- (start & 0x1f));
-
- nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
-
- return 0;
-}
-
-void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en,
- int popq_en)
-{
- int j, k, vc;
- int queue;
- uint64_t base;
-
- base = nlm_get_cms_regbase(node);
- for(j=0; j<1024; j++) {
- printf("Qid:0x%04d Val:0x%016jx\n",j,
- (uintmax_t)nlm_cms_get_onchip_queue (base, j));
- }
- /* Enable all cpu push queues */
- for (j=0; j<XLP_MAX_CORES; j++)
- for (k=0; k<XLP_MAX_THREADS; k++)
- for (vc=0; vc<CMS_MAX_VCPU_VC; vc++) {
- /* TODO : remove this once SMP works */
- if( (j == 0) && (k == 0) )
- continue;
- queue = CMS_CPU_PUSHQ(node, j, k, vc);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable pcie 0 push queue */
- for (j=CMS_PCIE0_QID(0); j<CMS_PCIE0_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable pcie 1 push queue */
- for (j=CMS_PCIE1_QID(0); j<CMS_PCIE1_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable pcie 2 push queue */
- for (j=CMS_PCIE2_QID(0); j<CMS_PCIE2_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable pcie 3 push queue */
- for (j=CMS_PCIE3_QID(0); j<CMS_PCIE3_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable DTE push queue */
- for (j=CMS_DTE_QID(0); j<CMS_DTE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable RSA/ECC push queue */
- for (j=CMS_RSA_ECC_QID(0); j<CMS_RSA_ECC_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable crypto push queue */
- for (j=CMS_CRYPTO_QID(0); j<CMS_CRYPTO_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable CMP push queue */
- for (j=CMS_CMP_QID(0); j<CMS_CMP_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable POE push queue */
- for (j=CMS_POE_QID(0); j<CMS_POE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable NAE push queue */
- for (j=CMS_NAE_QID(0); j<CMS_NAE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue, spill_en);
- }
-
- /* Enable all pop queues */
- if (popq_en) {
- for (j=CMS_POPQ_QID(0); j<CMS_POPQ_MAXQID; j++) {
- queue = CMS_POPQ(node, j);
- nlm_cms_config_onchip_queue(base, spill_base, queue,
- spill_en);
- }
- }
-}
-
uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
{
return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
@@ -453,94 +198,14 @@ void nlm_cms_per_queue_level_intr(uint64
val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+ val &= ~((0x7ULL << 56) | (0x3ULL << 54));
+
val |= (((uint64_t)sub_type<<54) |
((uint64_t)intr_val<<56));
nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
}
-void nlm_cms_level_intr(int node, int sub_type, int intr_val)
-{
- int j, k, vc;
- int queue;
- uint64_t base;
-
- base = nlm_get_cms_regbase(node);
- /* setup level intr config on all cpu push queues */
- for (j=0; j<XLP_MAX_CORES; j++)
- for (k=0; k<XLP_MAX_THREADS; k++)
- for (vc=0; vc<CMS_MAX_VCPU_VC; vc++) {
- queue = CMS_CPU_PUSHQ(node, j, k, vc);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all pcie 0 push queue */
- for (j=CMS_PCIE0_QID(0); j<CMS_PCIE0_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all pcie 1 push queue */
- for (j=CMS_PCIE1_QID(0); j<CMS_PCIE1_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all pcie 2 push queue */
- for (j=CMS_PCIE2_QID(0); j<CMS_PCIE2_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all pcie 3 push queue */
- for (j=CMS_PCIE3_QID(0); j<CMS_PCIE3_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all DTE push queue */
- for (j=CMS_DTE_QID(0); j<CMS_DTE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all RSA/ECC push queue */
- for (j=CMS_RSA_ECC_QID(0); j<CMS_RSA_ECC_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all crypto push queue */
- for (j=CMS_CRYPTO_QID(0); j<CMS_CRYPTO_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all CMP push queue */
- for (j=CMS_CMP_QID(0); j<CMS_CMP_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all POE push queue */
- for (j=CMS_POE_QID(0); j<CMS_POE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all NAE push queue */
- for (j=CMS_NAE_QID(0); j<CMS_NAE_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup level intr config on all pop queues */
- for (j=CMS_POPQ_QID(0); j<CMS_POPQ_MAXQID; j++) {
- queue = CMS_POPQ(node, j);
- nlm_cms_per_queue_level_intr(base, queue, sub_type, intr_val);
- }
-}
-
void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
int intr_val)
{
@@ -548,94 +213,14 @@ void nlm_cms_per_queue_timer_intr(uint64
val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
+ val &= ~((0x7ULL << 51) | (0x3ULL << 49));
+
val |= (((uint64_t)sub_type<<49) |
((uint64_t)intr_val<<51));
nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
}
-void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val)
-{
- int j, k, vc;
- int queue;
- uint64_t base;
-
- base = nlm_get_cms_regbase(node);
- /* setup timer intr config on all cpu push queues */
- for (j=0; j<XLP_MAX_CORES; j++)
- for (k=0; k<XLP_MAX_THREADS; k++)
- for (vc=0; vc<CMS_MAX_VCPU_VC; vc++) {
- queue = CMS_CPU_PUSHQ(node, j, k, vc);
- nlm_cms_per_queue_timer_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup timer intr config on all pcie 0 push queue */
- for (j=CMS_PCIE0_QID(0); j<CMS_PCIE0_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
- nlm_cms_per_queue_timer_intr(base, queue, sub_type, intr_val);
- }
-
- /* setup timer intr config on all pcie 1 push queue */
- for (j=CMS_PCIE1_QID(0); j<CMS_PCIE1_MAXQID; j++) {
- queue = CMS_IO_PUSHQ(node, j);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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