Author: adrian
Date: Thu Jul 21 08:35:10 2011
New Revision: 224243
URL: http://svn.freebsd.org/changeset/base/224243
Log:
Break out the PLL setup into (mostly) per-chip methods, rather than
polluting the AR5416 code with later chipset support.
Note: ar9280InitPLL() supports Merlin (AR9280) and later (AR9285, AR9287.)
Submitted by: ssgriffonu...@gmail.com
Approved by: re (kib)
Modified:
head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
head/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
head/sys/dev/ath/ath_hal/ar9002/ar9280.h
head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Jul 21 08:31:55
2011 (r224242)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Jul 21 08:35:10
2011 (r224243)
@@ -1423,60 +1423,20 @@ ar5416UpdateChainMasks(struct ath_hal *a
void
ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
- uint32_t pll;
-
- if (AR_SREV_MERLIN_20(ah) &&
- chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
- /*
- * PLL WAR for Merlin 2.0/2.1
- * When doing fast clock, set PLL to 0x142c
- * Else, set PLL to 0x2850 to prevent reset-to-reset variation
- */
- pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
- } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
- pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
- if (chan != AH_NULL) {
- if (IEEE80211_IS_CHAN_HALF(chan))
- pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_QUARTER(chan))
- pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
-
- if (IEEE80211_IS_CHAN_5GHZ(chan))
- pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
- else
- pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
-
- } else
- pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
- } else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
- pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
- if (chan != AH_NULL) {
- if (IEEE80211_IS_CHAN_HALF(chan))
- pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_QUARTER(chan))
- pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
-
- if (IEEE80211_IS_CHAN_5GHZ(chan))
- pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
- else
- pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
- } else
- pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
- } else {
- pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
- if (chan != AH_NULL) {
- if (IEEE80211_IS_CHAN_HALF(chan))
- pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
- else if (IEEE80211_IS_CHAN_QUARTER(chan))
- pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
-
- if (IEEE80211_IS_CHAN_5GHZ(chan))
- pll |= SM(0xa, AR_RTC_PLL_DIV);
- else
- pll |= SM(0xb, AR_RTC_PLL_DIV);
- } else
+ uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
+
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0xa, AR_RTC_PLL_DIV);
+ else
pll |= SM(0xb, AR_RTC_PLL_DIV);
- }
+ } else
+ pll |= SM(0xb, AR_RTC_PLL_DIV);
+
OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
/* TODO:
Modified: head/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c Thu Jul 21 08:31:55
2011 (r224242)
+++ head/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c Thu Jul 21 08:35:10
2011 (r224243)
@@ -86,6 +86,28 @@ ar9160AniSetup(struct ath_hal *ah)
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
+static void
+ar9160InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
+ else
+ pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
+ } else
+ pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
+
+ OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+ OS_DELAY(RTC_PLL_SETTLE_DELAY);
+ OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
+}
+
/*
* Attach for an AR9160 part.
*/
@@ -118,6 +140,7 @@ ar9160Attach(uint16_t devid, HAL_SOFTC s
/* XXX override with 9160 specific state */
/* override 5416 methods for our needs */
+ AH5416(ah)->ah_initPLL = ar9160InitPLL;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9160_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9160_adc_gain_cal;
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9280.h
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9280.h Thu Jul 21 08:31:55 2011
(r224242)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9280.h Thu Jul 21 08:35:10 2011
(r224243)
@@ -59,5 +59,6 @@ struct ath_hal;
HAL_BOOL ar9280SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
void ar9280SpurMitigate(struct ath_hal *,
const struct ieee80211_channel *);
-
+void ar9280InitPLL(struct ath_hal *ah,
+ const struct ieee80211_channel *chan);
#endif /* _ATH_AR9280_H_ */
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c Thu Jul 21 08:31:55
2011 (r224242)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c Thu Jul 21 08:35:10
2011 (r224243)
@@ -99,6 +99,39 @@ ar9280AniSetup(struct ath_hal *ah)
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
+void
+ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
+{
+ uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
+
+ if (AR_SREV_MERLIN_20(ah) &&
+ chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
+ /*
+ * PLL WAR for Merlin 2.0/2.1
+ * When doing fast clock, set PLL to 0x142c
+ * Else, set PLL to 0x2850 to prevent reset-to-reset variation
+ */
+ pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
+ } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+ pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
+ if (chan != AH_NULL) {
+ if (IEEE80211_IS_CHAN_HALF(chan))
+ pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+ else if (IEEE80211_IS_CHAN_QUARTER(chan))
+ pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+ if (IEEE80211_IS_CHAN_5GHZ(chan))
+ pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
+ else
+ pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
+ } else
+ pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
+ }
+
+ OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+ OS_DELAY(RTC_PLL_SETTLE_DELAY);
+ OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
+}
+
/* XXX shouldn't be here! */
#define EEP_MINOR(_ah) \
(AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
@@ -138,6 +171,8 @@ ar9280Attach(uint16_t devid, HAL_SOFTC s
/* XXX override with 9280 specific state */
/* override 5416 methods for our needs */
+ AH5416(ah)->ah_initPLL = ar9280InitPLL;
+
ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch;
ah->ah_configPCIE = ar9280ConfigPCIE;
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Thu Jul 21 08:31:55
2011 (r224242)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c Thu Jul 21 08:35:10
2011 (r224243)
@@ -136,6 +136,8 @@ ar9285Attach(uint16_t devid, HAL_SOFTC s
/* XXX override with 9285 specific state */
/* override 5416 methods for our needs */
+ AH5416(ah)->ah_initPLL = ar9280InitPLL;
+
ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
ah->ah_configPCIE = ar9285ConfigPCIE;
ah->ah_setTxPower = ar9285SetTransmitPower;
Modified: head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c Thu Jul 21 08:31:55
2011 (r224242)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c Thu Jul 21 08:35:10
2011 (r224243)
@@ -137,6 +137,8 @@ ar9287Attach(uint16_t devid, HAL_SOFTC s
/* XXX override with 9280 specific state */
/* override 5416 methods for our needs */
+ AH5416(ah)->ah_initPLL = ar9280InitPLL;
+
ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;
ah->ah_configPCIE = ar9287ConfigPCIE;
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